Semiconductor device

ABSTRACT

A semiconductor device in which a plurality of semiconductor elements are bonded onto at least one electrode pattern on an insulator substrate formed a plurality of electrode patterns on the main surface, each of the electrodes of the semiconductor element being electrically connected to the electrode pattern, the other surface of the insulator substrate being bonded to a heat dissipating base, the upper surface of the heat dissipating base being covered with a member for cutting off the semiconductor elements from the outer environment, terminals electrically connecting the electrodes on said insulator substrate and the electrode placed outside the cutoff member being provided, wherein the material of the heat dissipating base has a linear expanding coefficient larger than the linear expansion coefficient of the semiconductor element and smaller than three times of the linear expansion coefficient of the semiconductor element, and a thermal conductivity larger than 100 W/mK, the semiconductor elements being arranged on at least one electrode surface and in at least two regions divided by the other electrode surface on the insulator substrate.

BACKGROUND OF THE INVENTION

[0001] 1. Field of the Invention

[0002] The present invention relates to a semiconductor module and asemiconductor device using a power semiconductor element, and moreparticularly relates to a semiconductor device for inverter andconverter.

[0003] 2. Description of the Related Art

[0004] In various kind of motor control, GTOs (Gate Turn Off Thyristors)have been used in the field of large power and transistors have beenused in the field of small power. However, in recent years IGBTs(Insulated Gate Bipolar Transistors) are rapidly spreading in the fieldof GTO and transistor because of ease of use that large current can becontrolled by voltage signal. IGBTs are generally used in the form ofmodule. Today, there are various types. For instance, in three-phasemotor control, three phase and upper-arm/lower-arm currents need to beswitched. That is, three switches for upper arms, three switches forlower arms, total of six switches are required. Therefore, there are atype where IGBTs corresponding to one arm are mounted on a module, atype where IGBTs corresponding to six arms are mounted on a module, anda type where an additional circuit is further mounted.

[0005] As for structures, although there are proposed various ideas, anexample close to the present invention, in which IGBTs corresponding toone arm are mounted on a module, will be explained below.

[0006] Since plural chips of IGBT are used in connecting in parallelwhen a single chip cannot control a desired capacity of current, asemiconductor switching device mounting plural chips connected inparallel will be discussed.

[0007] A structure will be described below, according to a commonmanufacturing process. One surface of an IGBT chip is bonded on one ofCu thin plates, which are bonded on both surfaces of an alumina or AlNceramic substrate, using a solder having a highest melting point amongsolders to be used in the module. This Cu plate commonly becomes acollector terminal. On the other surface of the chip, an emitter and agate electrodes are formed. Both are wire-bonded to an emitter and agate terminal Cu thin plates formed on the same surface of the ceramicsubstrate as the collector terminal are formed, respectively. The Cuplate on the other surface of the ceramic substrate is bonded to acooling plate as a base of the module using solder. An Al or Cu plate iscommonly used for the cooling plate. Connection of the module externalterminals to the electrodes on the ceramic substrate is performed by Culeads integrally formed together with the external terminals. Theexternal terminal is usually called as a terminal block. A molded resincase is bonded to the metallic base (cooling plate) using an adhesive. Agel is injected through an aperture intentionally opened between thecase and the terminal block and hardened, and then above it a hard resinis injected and hardened. It is basically preferable to harden the gelafter sufficiently removing bubbles from the injected gel. However, ifremoving of bubbles is performed in this structure, the gel rises upalong the inner surface of the case to cause degradation of bondingbetween the hard resin and the case. Therefore, the hard resin isinjected without the important removal of bubbles.

[0008] The above is a common manufacturing process and a commonstructure of a module.

[0009] The module is attached to a proper cooling structure with boltsusing holes formed on the four corners of the metallic base. Since theelectric potential of the cooling structure is generally in groundpotential, insulation to the IGBT chip is performed by the ceramicsubstrate.

[0010] The external terminals are composed of a collector terminal, anemitter terminal, a gate terminal and an emitter auxiliary terminal forgate.

[0011] In the aforementioned conventional technology, there are problemsas follows.

[0012] (1) life-time of bonding solder between the metallic base and theceramic substrate: When a module is started to operate, heat isgenerated and shear stress is generated in the bonding solder due todifference of linear expansion coefficients between the metallic baseand the ceramic substrate. The solder is thermal-fatigued and thencracks progress inside the solder generally from the periphery to themetallic base. When the cracks are progressed to a certain degree andthe thermal resistance between the IGBT chip and the metallic base isincreased, the solder cracks are acceleratively progressed due toapplying of positive thermal feed-back on the solder cracks and finallythe module becomes incapable of operating.

[0013] (2) The gel plays a role of passivation by coating over the IGBTchip. When the hard resin allowed to flow over the gel is hardened, thechip is usually heated at nearly 150° C. At this time, the volume of thegel is expanded by approximately 10%. In the process of cooling aftercompletion of hardening, cracks are generated inside the gel because thecontraction of the gel volume is restricted by the case and the hardresin. This phenomenon can be confirmed by observing an actual productwith X-ray. If the cracks reach over the IGBT chip, the passivationeffect for the chip disappears.

[0014] (3) In a case of using modules connected in parallel, thegate-emitter circuit in the input circuit forms a loop. There are somecases where an oscillation phenomenon occurs due to inductance andfloating capacitance between the gates and between the emitters andinput capacitance.

[0015] (4) The external terminals are generally arranged in the lateraldirection of the module in order of collector terminal, emitterterminal, gate terminal and gate/emitter auxiliary terminal bystructural reason. In this arrangement, however, the external wiringbecomes complex and error operation probably occurs due to mutual noiseswhen a lot of modules are mounted as an inverter. Specially in a casewhere the modules are applied to an inverter for vehicle, the mountingspace in vertical direction should be decreased as low as possible sincethe inverter is installed under the floor. Therefore, the modules arepreferably mounted in arranging the shorter side direction of themodules to the vertical direction. In this case, the wiring becomescomplex when the conventional arrangement of the terminals is employed.

[0016] (5) In order to switching the modules at a high speed,inductances of the collector and the emitter should be decreased assmall as possible.

[0017] Although the above description regarding modules is problems on apower switching device, that is basically common problems on a currentcontrol device using semiconductors.

[0018] In the conventional technology, an insulator capacitancecomponent is generated at the portion where withdrawal or void isgenerated inside the solder bonding the metallic film and the insulatorsubstrate, or at the portion where a gap is provided between themetallic film and the insulator substrate. This insulator capacitancecomponent is connected to an insulator capacitance component due to theinsulator substrate in series. When a high voltage is applied to themodule is this case, a partial discharge (corona discharge) occurs inthe vacant layer where the insulator capacitance component occurs. Sincethe partial discharge during operation of the module deteriorates thefilling agent inside the module such as silicon gel, deterioration ofinsulation is caused at last. The partial discharge during switchingcauses noise, the noise causes error operation specially in a module ofinsulated gate type element such as IGBT.

[0019] However, when number of semiconductor elements in a module, it isdifficult to make the amount of current flowing each of the elementsuniform due to variation of characteristic of each elements anddifference in wiring length in side the module. When the non-uniformityin current occurs among the elements, spike noise occurs due to shift inON/OFF time among the elements during switching operation. There arisesa problem in that solder or the metallic wire of one element wherecurrent is concentrated is deteriorated in a short time comparing theother elements.

SUMMARY OF THE INVENTION

[0020] An object of the present invention is to solve the aforementionedproblems in the conventional technology. (1) Means to solve the problem(1) above is not only to suppress the amount of heat generation of theIGBT chip (the same can be said for a bipolar transistor and an MOStransistor), but also to select a ceramic substrate mounting the chipand a metallic base which have linear expansion coefficients close toeach other and to employ the metallic base material having a highthermal conductivity. Since the chip and the ceramic substrate arebonded with solder, the result is that it is important to match thelinear expansion coefficients of the chip, the ceramic substrate and themetallic base with one another. Since the thermal coefficient of thechip is approximately 3.5×10⁻⁶/° C., it is suggested that Mo is used forthe metallic base. However, the inventors have found that simply usingMo instead of Cu, which is conventionally used, leads three largeproblems.

[0021] The first problem is that a crack occurs in the ceramic at aposition under a Cu thin plate on the ceramic substrate where anelectrode terminal is bonded by solder. Since the linear expansioncoefficients of the ceramic substrate and the Mo plate are close to eachother, the thermal stress acting on the solder between the ceramicsubstrate and the Mo plate is decreased. That is, the ceramic substrateand the Mo plate are thermally deformed as if the both are formed of onematerial. Therefore, the thermal stress between the Cu thin plate on theceramic substrate and the ceramic substrate is increased. It has beenestimated from a result of thermal stress analysis that when a Cuterminal is attached onto the Cu thin plate, the thermal stress underthe terminal is extremely increased much more to cause cracks in theceramic under the Cu thin plate. Therefore, it is necessary to preventthe ceramic substrate from damage by suppressing the thermal deformationof the Cu thin plate and decreasing the thermal stress between the Cuthin plate and the ceramic substrate in such a structure that the Cuthin plate portion to be attached with the Cu terminal is not bonded tothe ceramic substrate, that is, in a floating state, or that the portionto be attached with the Cu terminal is not placed in the periphery ofthe Cu thin plate pattern, but is placed in the inner side of the Cuthin plate pattern, or that a material having a small linear expansioncoefficient such as Mo is inserted between the Cu terminal and the Cuthin plate.

[0022] The second problem is that loosening of fixing bolt or damage offixing bolt occurs by thermal deformation due to the difference inlinear expansion coefficients the metallic base of a semiconductordevice and the member to fix the semiconductor device. In order to solvethe problem, the thermal deformation described above is absorbed bydeformation of a bolt in such a structure that the length of the bolt islengthened by inserting a ring having a linear expansion coefficientclose to that of the bolt between the head of the bolt and the metallicbase.

[0023] The third problem is that there is no material of which linearexpansion coefficient is close to that of silicon and thermalconductivity is as large as that of Cu. Mo does not satisfy thiscondition. For instance, the thermal conductivity of Cu is approximately390 W/mK. On the other hand, the thermal conductivity of Mo isapproximately 140 W/mK which is about ⅓ of that of Cu. As far asconsidering the thermal resistance from the chip to the metallic base,this difference does not become a problem, but grease is usuallyinserted between external cooling members to attach a semiconductordevice in order to absorb bending of the external cooling members.However, since the thermal conductivity of grease is as low as 1 W/mK,in order to compensate the thermal resistance of the grease layer it isnecessary to diffuse heat generated inside the semiconductor device overthe whole area of the metallic base and then dissipate the heat from thelarge area through the grease layer. When Mo is used for the metallicbase, the heat transferred from the chip is not sufficiently diffusedand accordingly the heat has to be dissipated from a small area of themetallic base. This increases the thermal resistance. In order to avoidthis phenomenon, it is necessary to arrange the heat sources of thechips as sparse as possible.

[0024] (2) In order to prevent the crack in the gel described above inthe item of problem (2), it is necessary that the interface between thegel and the hard resin injected on the gel is separated when the hardresin is hardened. Although it is preferable that the surface of the gelis coated with a mold release agent, there is no proper material in thestate of the art.

[0025] With this being the situation, a space is provided above theupper surface of the gel so that the gel can freely expand and contract.In this case, it is a key point to maintain the hermeticity of thespace. The following structures are invented.

[0026] (i) The gap between the terminal and the mold in a terminal blockis coated with a high viscous resin or a hard resin to be described (ii)below.

[0027] (ii) The case and the block are engaged with a J-shapedstructure, and this portion is sealed using a hard resin.

[0028] Even if the above countermeasure for hermeticity is performed,countermeasure for condensation on the surface of the gel is requiredsince the case and so on are made of organic materials. Thereby, thefollowing method is invented. The terminal passes through the inside ofthe gel and the space. When condensation occurs on the surface of thegel, the withstanding voltage of insulation between the electrodes isdegraded on the surface of the gel. Therefore, the electrode in thespace is covered with the molding material for the terminal block sothat the lowermost covered portion is dipped into the gel. That is, theinvented structure is that the electrode inside the module is notexposed to the space.

[0029] (3) In order to suppress the oscillation phenomenon apt to occurin the parallel connection of the semiconductor device described abovein the item of the problem (3), it is effective to insert an externalresistor in the gate circuit. In this case, it is necessary to suppressthe external noise added to the gate circuit as low as possible. Theinvented terminal arrangement to suppress the noise due toelectromagnetic induction is that an auxiliary gate terminal is providedin the terminal block of the semiconductor switching device to decreasethe area formed by the gate circuit and the wire of the auxiliaryemitter circuit.

[0030] (4) As described above in the item of the problem (4), theinvented structure is that the collector and the emitter terminals arearranged in the direction of the shorter side of the module in order todecrease mounting area and simplify the wiring as an inverter.

[0031] (5) As described above in order to suppress the inductance of theelectrode terminal as small as possible, the following structures areinvented.

[0032] (i) In order to suppress the inductance of the electrode terminalsmall, the mechanical length of the terminal is made as short aspossible. The invented structure is that the collector and the emitterterminals are crossed with each other with spacing in the verticaldirection for keeping insulation inside the gel to shorten the length ofthe terminals.

[0033] (ii) As an alternative method, there is a method to decrease theeffective inductance utilizing the mutual inductance by considering thecurrent flow directions of the collector and the emitter terminals. Theinvented structure is that in order to suppress the inductance of theelectrode terminals small, the vertical wide width portions of thecollector and the emitter terminals are arranged in parallel to eachother since the current flows in the vertical position of the collectorand the emitter terminals are opposite to each other.

[0034] The circuit board according to the present invention comprises ameans for short-circuiting an insulator capacitance component which isgenerated at the portion where withdrawal or void is generated insidethe solder bonding the metallic film and the insulator substrate, or atthe portion where a gap is provided between the metallic film and theinsulator substrate.

[0035] In more detail, a first conductor layer is provided on one of thesurfaces of the insulator plate, and a second conductor layer isprovided in a position facing to the first conductor layer on theinsulator plate, consequently, the second conductor layer is provided inseparating from the first conductor. Further, the first conductor layerand the second conductor layer are electrically connected by aconductor.

[0036] In the semiconductor device according to the present invention,semiconductor elements are jointed to the first conductor layer on thecircuit board described above, and at the same time an insulatorcapacitance component is short-circuited by bonding a conductive base tothe other surface of the insulator substrate, that is, to the surface inthe opposite side of the first conductor layer.

[0037] The object of suppressing the partial discharge described abovecan be attained by filling a dielectric material in a gap between aninsulator plate of a circuit board and a conductor layer in a circuitboard such as DBC (Direct Bond Copper) board or a semiconductor devicehaving such a board.

[0038] In more detail, the circuit board according to the presentinvention comprises an insulator plate, a conductor layer placed on thesurface of the insulator plate, a dielectric layer provided in a gapportion between the insulator plate and the conductor layer. Therein,the following relationship exists among the dielectric constant of thedielectric layer ∈_(g), the dielectric constant of the insulator plate∈_(b), the thickness of the gap portion L_(g), and the thickness of theinsulator plate L_(b).

∈_(g)≧∈_(b)×(L_(g)/L_(b))  (Equation 1)

[0039] There, ∈_(g) and ∈_(b) are in the same unit, and L_(g) and L_(b)are also in the same unit.

[0040] In the semiconductor device according to the present invention,semiconductor elements are jointed to the conductor layer on the circuitboard having the structure described above, and at the same time thecircuit board is jointed to a conductive support base. Further, in thesemiconductor device according to the present invention, a fluiddielectric material is filled in the device so as to adjoin to theinsulator plate and the conductor layer of the circuit board contained.

[0041] The semiconductor module to attain the object described abovecomprises a substrate made of an insulator, a plurality of semiconductorelements arranged on the insulator substrate, external connectingterminals electrically connected to an external apparatus, a conductorpattern formed on the insulator substrate, jointed with the externalconnecting terminals as well as electrically connected with theelectrodes of the plurality of semiconductor elements in parallel toform a current path from the external connecting terminals to theplurality of semiconductor elements, wherein the conductor pattern isformed symmetrically in regard to a certain phantom line on theinsulator substrate, a plurality of positions on the phantom line andsymmetrical in regard to the phantom line being used as jointing zonesfor the external connecting terminal, current bypass portions to makethe individual current paths of the plurality of semiconductor elementsin a nearly equal length being provided, the current bypass portion isformed by cutting away a path between a semiconductor element and thejointing zone and providing a bypass for allowing current to flowbetween the semiconductor element and the jointing zone when thedistance between the electrode of the semiconductor element and thejointing zone is shorter than the distances between the electrodes ofthe other semiconductor elements and the jointing zones. In a case wherethe semiconductor element has plural electrodes or an expandedelectrode, the averaged distance is taken as the distance between theelectrode of the semiconductor element and the jointing zone.

[0042] Further, the semiconductor module to attain the object describedabove comprises a substrate made of an insulator, a plurality ofsemiconductor elements arranged on said insulator substrate, externalconnecting terminals electrically connected to an external apparatus, aconductor pattern formed on the insulator substrate, jointed with theexternal connecting terminals as well as electrically connected with theelectrodes of the plurality of semiconductor elements in parallel toform a current path from the external connecting terminals to theplurality of semiconductor elements, wherein the external connectingterminal comprises a facing portion on the conductor pattern, the facingportion being parallel to and facing to the zone of each of the currentpaths for each of the semiconductor elements, the direction of currentflow in the facing portion being opposite to the direction of currentflow in each of the current paths.

[0043] By forming a conductor pattern symmetrical in regard to aspecified phantom line as the center line and symmetrically arranging aplurality of semiconductor elements, the current path length concerninga semiconductor element on the right hand side and the current pathlength in relation to a semiconductor element on the left hand sidebecome equal to each other, the inductances of the both current pathsalso become equal, and consequently the same current can flow both inthe element on the right hand side and in the element on the left handside. However, even if plural semiconductor elements are symmetricallyarranged, for example, in a case of three semiconductor elements, thecurrent flowing in a semiconductor placed in the center is differentfrom the current flowing in the other semiconductor element. In moredetail, in a case where number of semiconductor elements is three andthe junction zone for the external connecting terminals are placed onthe phantom line for symmetrical standard, the current path lengthconcerning the semiconductor element in the center is shorter than thecurrent path length in relation to the other semiconductor elements, theinductance of the current path in relation to the semiconductor elementplaced in the center is also smaller than the inductances of the currentpath in relation to the other semiconductor elements, and consequentlycurrent flows much in the element placed in the center.

[0044] In the present invention, a plurality of semiconductor elementsare symmetrically arranged, and current bypass portions to make theindividual current paths of the plurality of semiconductor elements in anearly equal length being provided. The current bypass portion is formedby cutting away a path between a semiconductor element and the jointingzone and providing a bypass for allowing current to flow between thesemiconductor element and the jointing zone when the distance betweenthe electrode of the semiconductor element and the jointing zone isshorter than the distances between the electrodes of the othersemiconductor elements and the jointing zones. As the result, theinductance of a current path in relation to a semiconductor element inwhich much current flows is increased and becomes equal to theinductance of the current paths in relation to the other semiconductorelements. The same quantity of current flows in each of all thesemiconductor elements. In more detail, in a case of threesemiconductors, a current bypass portion is formed by cutting away theconductor pattern between a semiconductor element and the jointing zonefor the external connecting terminal and providing a bypass for allowingcurrent to flow between the semiconductor element placed in the centerand the jointing zone. By lengthening the current path in relation tothe semiconductor element placed in the center, the length of currentpath becomes equal to the length of the current path in relation to theother semiconductor elements. By doing so, the same quantity of currentflows in each of all the semiconductor elements.

[0045] When current flows in a pair of parallel wires in the oppositedirections to each other, each of the inductance of the wire is mutuallycanceled. Therefore, in a case where a facing portion in facing to theconductor pattern is formed in the external connecting terminal, theinductance in the region of each of the current paths for pluralsemiconductor elements and the inductance in the facing portion of theexternal connecting terminal are mutually canceled. In this reason, evenif there are differences among the lengths of current paths in theconductor pattern for the plural semiconductor elements, there is almostno difference among the inductances of the current paths andconsequently the same quantity of current can be conducted in each ofthe semiconductor elements.

[0046] A semiconductor device, especially, a semiconductor large currentswitching device is subjected to large temperature difference and largenumber heat cycles. Therefore, the most important problem is to keep thelife time against fatigue of solder bonding between the members used.The fundamental measure is to decrease the strain occurred in the solderto extend the life time against thermal fatigue by closing the linearexpansion coefficients of the members used. With this measure, the threemain problem described above must be overcome at a time. The long lifetime can be attained by performing the following three measures at atime, that is, (1) measure for crack produced in the ceramic substrateunder a terminal, (2) dispersion of heat sources, (3) measure todecrease deformation of the fixing bolt. However, whether all themeasures are required at a time or not is determined by the reliabilityrequired for a product. As for the resolution of the item (1), byseparating the Cu thin plate under a terminal from the ceramicsubstrate, that is, in the state of so-called counter-beam, the Cu thinplate easily deforms so that stress does not occur between the ceramicsubstrate and the Cu thin plate. Another method is that the terminal isnot bonded at the end portion of the Cu thin plate pattern, but at aposition inside from the end portion by the distance of twice of the sumof the thickness of the terminal and the thickness of the Cu thin plate.By doing so, the problem to decrease the stress in the end portion ofthe Cu thin plate pattern can be solved. As a further method, a metalhaving a linear expansion coefficient close to that of the ceramicsubstrate is inserted between the terminal and the Cu thin plate. Bysandwiching the Cu thin plate, the Cu thin plate burdens most part ofthe thermal deformation to decrease the thermal stress on the surface ofthe ceramic substrate under the terminal. As for the item (2), it isnecessary to disperse chips generating heat at the same time by makingthe Cu thin plate patter on the ceramic substrate proper without degradethe electrical characteristics. As for the item (3), the key point is todecrease the stress produced in the bolt. A collar made of a materialhaving a linear expansion coefficient nearly equal to the linearexpansion coefficient of the fixing bolt is inserted between the head ofbolt and the metallic base. By lengthening the length of the bolt andthermally deforming the collar, the stress produced in the bolt isdecreased.

[0047] In the conventional technology, the gel crack measure is a largeproblem. When crack reach to the surface of a chip, the passivationeffect by gel disappears. Since the main cause to produce cracks is inthe structure to impede the contraction of gel, the fundamental measureis to provide a space over the gel. This method has a bad reaction. Itis necessary to keep the hermeticity of the space and to keep theinsulation between the terminals. It is necessary to suppress raising-upphenomenon of gel along the case wall at injecting and hardening the gelwhich impedes the wetness of the hard resin between the terminal and thecase. The measure against this phenomenon is that the injection andhardening of the gel is performed after the injection and hardening ofthe hard resin. The insulation between the terminals is kept by coveringthe portions of the terminals exposed in the space with a moldingmaterial. By doing so, it is also possible to reduce the weight of thedevice.

[0048] In the circuit board according to the present invention, even ifan insulating capacitance component is generated between the firstconductor layer and the insulator substrate by occurrence of withdrawalor void of the solder or by providing a gap, the insulating capacitancecomponent is short-circuited by the second conductor layer and theconductor. Therefore, since voltage is not applied to the insulatingcapacitance component, the partial discharge can be prevented.

[0049] Further, in the semiconductor device according to the presentinvention having such a circuit board, deterioration of the filler dueto partial discharge and error operation of semiconductor element can beprevented. Thus, the reliability of the semiconductor device can beimproved.

[0050] In the circuit board, the insulating capacitance component(C_(b)) by the portion of the insulator plate contacting to the gap andthe insulating capacitance component (C_(g)) by the gap are connected inseries. Therefore, when voltage (V_(I)) is applied to the circuit boardof a semiconductor device mounting the circuit board, the voltage issplit into each of the insulating capacitance components. Therein,according to the present invention, since a dielectric material isfilled in the gap and the insulating capacitance component of thisportion is, therefore, increased, the voltage (V_(g)) split in the gapcan be decreased (V_(g)=V_(I)×C_(b)/(C_(g)+C_(b))). Accordingly, thepartial discharge in the gap can be suppressed.

[0051] Where C_(b) is proportional to ∈_(b)/L_(b) and C_(g) isproportional to ∈_(g)/L_(g). Therefore, when the relation expressed bythe equation 1 is satisfied, C_(g) can be larger than C_(g). Thus thepartial discharge in the gap can be certainly suppressed by decreasingV_(g) smaller than the voltage split in the insulator plate.

[0052] Further, by filling the semiconductor device with a fluiddielectric material, the dielectric material flows into a gap in acircuit board caused by separation of a conductor layer or crack of theinsulator plate. Thus the partial discharge in the gap can besuppressed.

BRIEF DESCRIPTION OF THE DRAWINGS

[0053] FIGS. 1(a) and 1(b) are external views of a semiconductor devicein accordance with the present invention, where 1(a) is a perspectiveview and 1(b) is a plan view.

[0054]FIG. 2(a) is a view showing the internal structure of asemiconductor device in accordance with the present invention, and 2(b)is a view showing the details of the terminals.

[0055]FIG. 3 is a cross-sectional view showing the terminal connectingportion of the substrate of a semiconductor device in accordance withthe present invention.

[0056]FIG. 4 is a cross-sectional view showing a semiconductor device inaccordance with the present invention.

[0057]FIG. 5(a) is a plan view showing the corner of the attachingportion of a semiconductor device in accordance with the presentinvention, and 5(b) is a cross-sectional view of the corner of theattaching portion.

[0058]FIG. 6 is an explanatory view showing deformation of a fixingbolt.

[0059]FIG. 7(a) is a plan view showing a ceramic substrate in asemiconductor device in accordance with the present invention, and 7(b)is an equivalent circuit diagram of the circuit formed on the ceramicsubstrate.

[0060]FIG. 8 is a view showing an inverter mounting semiconductordevices in accordance with the present invention.

[0061]FIG. 9 is an equivalent circuit diagram of the inverter shown inFIG. 8.

[0062]FIG. 10 is a cross-sectional view showing the structure of anotherembodiment of a semiconductor device in accordance with the presentinvention.

[0063]FIG. 11(a) is a view showing another embodiment of a terminalportion, and 11(b) is a graph showing the shear force in the surface ofthe ceramic substrate under a terminal.

[0064]FIG. 12 is a view showing another embodiment of a semiconductordevice in accordance with the present invention.

[0065]FIG. 13 is a view showing another embodiment of a semiconductordevice in accordance with the present invention.

[0066]FIG. 14(a) is a partial view showing an embodiment of asemiconductor device in accordance with the present invention whichmounts a circuit substrate having a dielectric layer around a metallicfilm, and 14(b) is a cross-sectional view of the device.

[0067]FIG. 15(a) is a cross-sectional view showing the structure, and15(b) is a diagram showing the equivalent circuit of an embodiment inaccordance with the present invention.

[0068]FIG. 16(a) is a view showing another embodiment in accordance withthe present invention, and 16(b) shows a case where a crack is producedin the insulator plate.

[0069]FIG. 17 is a table showing the dielectric constants of variousinsulating materials.

[0070]FIG. 18 is a perspective view showing the first embodiment of asemiconductor module in accordance with the present invention (thecasing is omitted).

[0071]FIG. 19 is a cross-sectional view showing the first embodiment ofthe semiconductor module in accordance with the present invention.

[0072]FIG. 20 is a cross-sectional view taking the plane along the lineA-A in FIG. 19.

[0073]FIG. 21 is an explanatory view showing the shape of conductorpattern and the configuration of diode elements in the first embodimentof the semiconductor module in accordance with the present invention.

[0074]FIG. 22 is an explanatory view showing the current path in thefirst embodiment of the semiconductor module in accordance with thepresent invention.

[0075] FIGS. 23(a)-23(e) are explanatory views showing the layout ofsemiconductor elements in a semiconductor module. 23(a) is a case wherethere is a current cut-off pattern in a metallic film, and number ofsemiconductors is one. 23(b) is a case where there is no current cut-offpattern in a metallic film, and number of semiconductors is one. 23(c)is a case where there is a current cut-off pattern in a metallic film,and number of semiconductors is two. 23(d) is a case where there is nocurrent cut-off pattern in a metallic film, and number of semiconductorsis two. 23(e) is a case where there is a current cut-off pattern in ametallic film, and number of semiconductors is two.

[0076]FIG. 24 is a graph showing the relationship between distancebetween wires in parallel wiring and mutual inductance.

[0077]FIG. 25 is a perspective view showing the second embodiment of asemiconductor module in accordance with the present invention.

[0078]FIG. 26 is an explanatory view showing the shape of conductorpattern and the configuration of diode elements in the second embodimentof the semiconductor module in accordance with the present invention.

[0079]FIG. 27 is a perspective view showing the third embodiment of asemiconductor module in accordance with the present invention.

[0080]FIG. 28 is a cross-sectional view taking the plane along the lineB-B in FIG. 27.

[0081]FIG. 29 is a perspective view showing the fourth embodiment of asemiconductor module in accordance with the present invention.

[0082]FIG. 30 is a perspective view showing the fifth embodiment of asemiconductor module in accordance with the present invention.

[0083]FIG. 31 is a front view showing the sixth embodiment of asemiconductor module in accordance with the present invention.

[0084]FIG. 32 is a schematic view showing the connecting terminals inthe connector side in the sixth embodiment of the semiconductor modulein accordance with the present invention.

[0085]FIG. 33 is a diagram explaining the equivalent circuit of theconnecting terminals in the connector side in the sixth embodiment ofthe semiconductor module in accordance with the present invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0086] An embodiment of the present invention will be described below,referring to FIGS. 1(a) and (b). FIG. 1(a) is a perspective view showinga semiconductor device in accordance with the present invention and (b)is its plan view. The reference character 11 is a terminal block. Theterminal block comprises an emitter terminal 15 a which is a mainelectrode terminal, a collector terminal 15 b, an insulator plate 20 toobtain insulating withstanding voltage between the both electrodes, agate terminal 17, gate auxiliary terminals 18, 19, (the gate auxiliaryterminals 18, 19 are usually short-circuited and a oscillationpreventing gate resistor is connected between the gate auxiliaryterminal 19 and the gate terminal 17.), and rubber caps 21 a, 21 b tokeep the hermeticity of a space under the terminal block. The referencecharacter 12 is a case which is fixed with the terminal block using ahard resin 14 a. The reference characters 14 b, 14 c, 14 d, 14 e arehard resin foe keeping hermeticity between the electrodes and theterminal block. The reference character 13 is a metallic base. Thereference characters 23 a, 23 b are embedded nuts embedded in the case.The metallic base 13 and the case 12 are fixed to each other with anadhesive (not shown) and the embedded nut 23 a, 23 b using screws. Thereference characters 22 a, 22 b, 22 c, 22 d are collars for extendingthe length of bolts attached to holes for fixing the semiconductordevice to an external heat dissipating plate. Mo is used for themetallic base 13. However, since even the thermal conductivity of Mo isnot sufficient, other materials such as Al/SiC composite material,Cu/SiC composite material, Cu/BN composite material may be used. Thephysical properties which the metallic base should have is determined bythe condition of reliability of an object to which the current controldevice is used. There is no clear condition, such as acceptablecondition of linear expansion coefficient being lager than a certainvalue or unacceptable condition of linear expansion coefficient beingsmaller than a certain value. As for a semiconductor device for vehicle,the load condition is sever and the required life time of the product ismore than 20 years. According to an experimental result, it ispreferable that the linear expansion coefficient is smaller thanone-half of that of Cu, that is, 6×10⁻⁶/° C. and larger than that of Si,that is, 3.5×10⁻⁶/° C.; the thermal conductivity is larger than onefourth of that of Cu, that is, 100 W/mK.

[0087] The gate external resistor is connected between the gateauxiliary terminal 19 and the gate terminal 17. An external gate circuitis connected to the gate auxiliary terminal 18. In a case where asemiconductor device is used as a one unit, the external gate circuit isdirectly connected to the gate terminal 17. Since the gate auxiliaryterminals 18 and 19 are placed on the terminal block, both of theelectrode terminals can be closely arranged.

[0088] An internal structure will be described mainly on the terminal ofa semiconductor device according to the present invention in detail,referring to FIG. 2(a) and FIG. 2 (b). The reference character 201 a 201b are AlN ceramic substrates. Cu thin plates are bonded onto almost thewhole surfaces of the AlN ceramic substrates 201 a, 201 b in the side ofthe metallic base 13 directly or using a solder added with activationmetal such as Ti. The metallic base 13 and the Cu thin plates on the AlNceramic substrates 201 a, 201 b are bonded using a eutectic solder. Theother side surfaces of the AlN ceramic substrates 201 a, 201 b are alsobonded with Cu thin plate as the same as described above. However, theCu thin plate on these surfaces are patterned in the collector zones 202a, 202 b, the emitter zones 203 a, 203 b, and the gate zones (notshown). An IGBT chip (not shown) is connected onto a proper position ofthe collector pattern using solder. The collector pattern is dividedinto two zones on the substrate, and the two zones are connected with athin Cu thin plate 204 a or 204 b. The collector terminal 15 b isconnected with connecting portions 205 a, 205 c, and 206 b, 205 d to theCu thin plate pattern 202 a, 202 b using a eutectic solder. The emitterpattern 203 a, 203 b and the emitter terminal 15 a are connected atemitter terminal connecting positions 207 a, 207 b to the Cu thin platepattern 203 a, 203 b using a eutectic solder. The collector electrodeterminal 15 b passes through under and crosses with the emitter terminalso that its length becomes short. The rising portions 208 a, 208 b ofthe collector and the emitter terminals are arranged in side by side.

[0089] In this embodiment, AlN is used for the ceramic substrate. Thereason to use AlN is that the linear expansion coefficient of AlN is5.7×10⁻⁶/° C. and close to that of Si, and the thermal conductivity islarger than 100 W/mK. However, since the thickness of the substrate isgenerally as thin as 0.6 mm, the thermal resistance does not become solarge even if alumina is used. Therefore, alumina may be used if thepower consumption of semiconductor is small.

[0090] Holes 209 a, 209 b, 209 c, 209 d (not shown) in the corners ofthe metallic base 13 are for fixing the semiconductor device to anexternal cooling member.

[0091] Further, the cross-sectional structure of the collector terminalconnecting position, foe example, 205 a will be described in detail,referring to FIG. 3. Description will be made referring to the figurethough there are some overlapping explanations. The Cu thin platepattern 302 is bonded onto almost the whole bottom surface of the AlNceramic substrate 13, and the Cu thin plate pattern and the metallicbase 13 are bonded using a eutectic solder (the bonding layer betweenthe Cu thin plate and the AlN ceramic substrate is omitted toillustrate). On the other hand, the Cu thin plate pattern is bonded tothe other surface of the AlN ceramic substrate 201 with layer 304 of asolder added with Ti. The collector terminal connecting position 205 isbonded to the Cu thin plate pattern 202 a using a eutectic solder 306.In the bonding portion under the Cu thin plate pattern, there is formeda gap 305 where the Cu thin plate pattern is not bonded. Further, ametallized layer 303 made of silver solder added with Ti is formed onthe surface of the ceramic substrate in the gap portion.

[0092] In FIG. 14, metallic films 31, 32 made of copper are bonded ontoeach of the surfaces of an insulator plate 33 made of aluminum nitrideusing a bonding material 34 made of silver as the main composition.There, the metallic film 31 is a first conductor layer which is wiringto form a circuit. The metallic films 31, 32, the insulator plate 33 andthe bonding material 34 compose a so-called DBC board 56. Further, inthe zone 57 where the insulator plate 33 and the metallic film 31 arenot bonded, a layer 38 of conductor, that is, a second conductor layeris provided on the surface of the insulator plate 33 facing to themetallic film 31. Here, the layer 38 of conductor contacts to thebonding material 34. Therefore, the metallic films 31 and 32 areelectrically connected to each other by the bonding material 34 ofconductor.

[0093] A semiconductor element 37 is bonded on the metallic film 31 ofthe circuit board having such a construction using a solder 36. Further,the metallic film 32 and a conductive supporting board 30 made of ametal are bonded using a solder 35 having lead and tin as the maincomponents. Such a supporting board mounting the circuit board bonding asemiconductor element is contained in an enclosed case to form asemiconductor module. In this embodiment, the semiconductor element 37and the supporting board 30 are insulated by the insulator plate 33. Inthis embodiment, there are produced an insulating capacitance componentby the insulator plate 33, that is, an insulating capacitance component39 (C_(A2)) in a zone 59 bonded with the metallic film 31 and aninsulating capacitance component 41 (C_(A1)) in a zone 57 not bondedwith the metallic film as well as an insulating capacitance component 40(Cd) by the gap between the metallic film 31 and the insulator plate 33in a zone 57. C_(A1) and C_(A2) are connected in parallel by themetallic film 32, the layer 38 of conductor and the bonding material 34,and Cd is connected to this parallel circuit in series by the layer 38of conductor and the bonding material 34. When voltage 43 V1 is appliedto a module, voltage (Vd) is applied to Cd if the circuit is formedsimply by connecting Cd in series to a parallel circuit of C_(A1) andC_(A2). At that time, if the gap forming Cd is an air layer or a vacuumlayer, Vd becomes large to cause partial discharge because of a smalldielectric constant. However, in this embodiment, Cd is short-circuitedby the metallic film 31, the layer 38 of conductor and the bondingmaterial 34. Therefore, Vd can be decreased and consequently the partialdischarge can be suppressed.

[0094] In the above embodiment, in order to certainly suppress thepartial discharge, it is necessary to form the layer of conductor so asnot to form defects or separations such as pinholes. Although the vapordeposition method or the metallizing method is suitable as the filmforming method, the metallizing method is preferable to increase thestrength of contact between the insulator plate and the layer ofconductor to prevent separation. However, it is not limited to thesemethod as far as no defect and better capability of contact. As tomaterials for the film, a laminated film such as Au/Pt/Ti/AlN, Pt/Ti/AlNor a single component film may be employed. With considering thecapability of contact to the insulator plate, a metallized film using Wor a Mo—Mn alloy is preferable, but not limited. Further, by applying aclosed-grained plating such as Ni plating on each of the metallizedfilms, it is possible to eliminate defects such as pinholes.

[0095] The materials for the insulator plate, the metallic film and thebonding member are not limited to the materials described in theembodiments, it is possible to use various kinds of insulators for theinsulator plate, and various kinds of conductors for the metallic filmand the bonding member. The insulator plate and the metallic film may bebonded to each other by heating while the metallic film and theinsulator plate are contacting to each other without using metallicsolder. The insulator plate may be directly bonded onto the supportingboard using a bonding material instead of attaching a metallic film ontothe surface of the supporting board side of the insulator plate.

[0096] The structure will be described, referring to a cross-sectionalview taking the plane along the line A-A′ of FIG. 1(b). FIG. 4 is thecross-sectional view. The reference character 11 is the terminal block,the reference character 12 is the case, the reference character 13 isthe metallic base, the reference character is the insulator plate, thereference character 15 a is the emitter terminal, the referencecharacter 15 b is the collector terminal, the reference characters 201a, 201 b are the AlN ceramic substrates, the reference characters 207 a,207 b are the emitter terminal connecting positions, the referencecharacter 401 is a terminal cover mold member for covering the risingportion of the terminal and the lower end of the terminal cover moldmember is dipped into the gel 407. The structural characteristics of thepresent invention will be described according to the manufacturingprocess.

[0097] The hermeticity between the terminal and the terminal cover moldmember is obtained through two-stage resin injection. Initially, interminal block manufacturing process, by injecting a resin 405 having acomparably high viscosity between the terminal block and the terminal,the both are fixed to each other without allowing the resin to flow out.By doing so, a terminal block having a high hermeticity can be obtained.The AlN ceramic substrates 201 a, 201 b connected with IGBT chip (notshown) are bonded onto the metallic base 13 using a solder. Next, theterminal block 11 is connected to the AlN ceramic substrates 201 a, 201b through the emitter terminal connecting positions 207 a, 207 b using asolder. After cleaning, the case 12 is bonded to the periphery of themetallic base 13 using an organic adhesive agent 406. A first hard resin404 is injected into a coupling portion 402 for the terminal block andthe peripheral terminal block of the case and a coupling portion 403 forthe case without over-flowing and is hardened. Then, a second hard resin14 a is injected into the coupling portion for the case and hardened. Ahard resin 14 b is injected into the terminal portion and hardened.Next, the silicone gel 407 is injected through a hole to fit a rubbercap 21 a using a level gauge, and bubble removal is performed and thenthe silicon gel is hardened. It is clarified that in order to performcomplete bubble removal, it is important not to contact the silicone gel407 to the terminal block coupling portion 402 during removing bubbles.Finally, the rubber cap is fit to the hole and the assembling work iscompleted.

[0098] By the process and the structure described above, the followingcharacteristics in regard to hermeticity can be obtained.

[0099] (i) Since the case and the terminal block are bonded using a hardresin before performing removal of bubbles, jointing failure of caseusing a hard resin due to raising-up of the gel along the wall iseliminated. Therefore, the hermeticity can be substantially improved.

[0100] (ii) Since a space can be provided above the surface of the gelby employing the coupling structure between the case and the terminalblock described above, the interfering factor with hardening contractionof the gel is only the wall of the case and the gel can be almost freelycontracted, and consequently there is no crack the gel, which isdifferent from the conventional structure.

[0101] (iii) Since the space 408 is filled with the hard resin in theconventional structure, the weight of the device is very heavy. On thecontrary, in the present invention, since the space can be made as anair layer, the weight of the device is light.

[0102] A further invention in regard to structure will be described,referring to FIG. 5. FIG. 5(a) is a plan view showing the corner of theattaching portion of a semiconductor device, and (b) is itscross-sectional view. In order to inject the first hard resin 404described above without allowing to overflow, it is necessary toaccurately control the level of the hard resin. Therefore, a setbackportion 410 is provided, and the bottom of the setback portion 410 isused as the level for the first hard resin. By doing so, the first hardresin can be accurately injected and accordingly the trouble in overflow of the first hard resin 404 is completely eliminated duringassembling. Although the setback portion 410 is provided in the cornerof the case in the embodiment, the position is not limited to thecorner.

[0103]FIG. 15 shows the cross-sectional structure and the equivalentcircuit of an embodiment in accordance with the present invention. Themetallic films 31, 32 made of copper are bonded onto each of thesurfaces of an insulator plate 33 made of aluminum nitride havingthickness of 635 μm using a bonding material 34 made of a metallicsolder having thickness of nearly 100 μm. This DBC board is bonded onthe metallic supporting board 30 using solder 35. Further, asemiconductor element 37 is bonded onto the metallic film 31 on theinsulator plate 33 using solder 36. There, the metallic film 31 becomesa circuit wiring pattern. There is a gap between the insulator plate 33and the metallic film 31 where the both are not bonded with the bondingmember 34. A dielectric material 44 is provided in the gap. An externalterminal, not shown, is bonded on the metallic film 31 in the positionof the gap. In this structure, even if a stress is applied to theexternal terminal, the stress is absorbed by the bending of the metallicfilm 31. Therefore, separation and crack are hardly occur in theterminal connecting portion.

[0104] The semiconductor element 37 and the metallic supporting board 30are insulated by the insulator plate 33 inside the module. Theinsulating capacitance is determined by the distance between the endportion of the metallic film 31 in the circuit side and the end portionof the insulator plate 33, or the insulating capacity component 45 bythe insulator plate 33. In the portion (zone 57) where the metallic film31 and the insulator slate 33 are not bonded, an insulating capacitancecomponent 46 is produced by the gap between the metallic film 31 and theinsulator plate 33. When a voltage 43 V1 is applied to the module, avoltage Vg is split to the insulating capacitance 46 by the gap. In thisembodiment, by inserting silicon rubber into the gap as a dielectricmember 44, the voltage Vg applied between the both ends of theinsulating capacitance component 46 of the gap is decreased lower thanthe voltage applied to the both ends of the insulating capacitancecomponent 47 of the insulator plate 33 arranged in series to the aboveinsulating capacitance component. Thereby, occurrence of the partialdischarge is prevented.

[0105] There, since the dielectric constant of aluminum nitride (AlN) is8.9 as shown in the table of FIG. 17, it is required from the equation(1) that the dielectric constant of the dielectric member is nearly 1.4.Since the dielectric constant of silicone rubber is 2.8 as shown in thetable, the equation (1) is sufficiently satisfied.

[0106] By using silicone gel commonly used for coating and protectingsemiconductor elements in a module as the dielectric member, occurrenceof the partial discharge can be also prevented. In this case, the moduleassembling process can be simplified since the coating material and thedielectric member 44 are of the same material. Further, since the wholesurface of the metallic film 31 can be coated with silicone gel,discharge due to concentration of electric field in the edge portions ofthe metallic film can be also suppressed.

[0107] As for the method of injecting dielectric material in a gap,there are various methods such as resin injection in vacuum, vacuumde-bubbling after injection, resin heating during injection fordecreasing viscosity. Further, there is a method where resin is droppeda portion of a gap between the metallic film 31 and the insulator plate33 to inject the resin utilizing the capillary phenomenon.

[0108]FIG. 16 shows another embodiment according to the presentinvention. The embodiment is for preventing the partial discharge when aDBC board is deteriorated during operation of the module. FIG. 16(a)shows a case where a separation occurs in the interface between thebonding member 34 and the insulator plate 33. At that time, aninsulating capacitance component 49 is newly produced in the separationzone 48 by the separated gap in addition to the insulating capacitancecomponent 58. However, by placing a fluid insulator member 50 (fluiddielectric material) such as silicone oil in the portion adjacent to thebonding layer, the partial discharge cannot occur even in the separatedportion since the fluid insulator member 50 flows into the gap newlyproduced after assembling of the module. FIG. 16 (b) shows a case wherea crack 52 is produced in the insulator plate 33. The insulatingcapacitance component in the zone 51 where the crack occurs is splitinto three insulating capacitance components 53, 54, 55 due to the crackin the insulator plate 33. Partial discharge is apt to occur speciallyin the insulating capacitance component 54 since the portion is a gapproduced by the crack. However, since the fluid insulator member isarranged in the portion adjacent to the insulator plate, the partialdischarge cannot occur as the same as in FIG. 16 2(a).

[0109] These defects are caused near the metallic film 31 in themounting side of the semiconductor element. However, there is apossibility that deterioration occurs in the side of the modulesupporting board. In this case, the partial discharge can be preventedby arranging the fluid insulator member in the portion adjacent to thebonding member 34 and the insulator plate 33.

[0110] An invention in relation to prevention of loosing of fixing boltwill be described below, referring to FIG. 6. In this figure,unnecessary portions for explaining are omitted. the reference character13 is the metallic base, the reference character 22 is the collar, thereference character 411 is an external cooling member, the referencecharacter 412 is a thermal conducting grease applied between themetallic base 13 and the external cooling member 411, the referencecharacter 413 is a fixing bolt, and the reference character 414 is awasher. Now, let consider a case where the environmental temperature israised. Cu or Al is commonly used for the external cooling member 411 Onthe other hand, the linear expansion coefficient of the metallic base issmall and near that of silicon as described above. Therefore, theexternal cooling member 411 expands larger than the metallic base. Theexternal cooling member 411 can easily slide against the metallic basebecause of existence of the grease 412.

[0111] When there is a collar 22, the thermal stress acting on the boltis moderated by deformation of the collar itself. At that time, if thesliding force acting between the head of the bolt and the collar issmaller than the friction force between the both, the bolt is notloosed. In addition to this, the shearing stress acting on the bolt isalso moderated and accordingly the bolt is not damaged. It is alsopreferable that the load acting on the bolt in its axial direction isnot varied. Therefore, since the deformation of the collar and themetallic base preferably balances with the axial deformation of thebolt, the condition required for the linear expansion coefficient of thecollar is equal to or larger than that of the bolt.

[0112] Arrangement of IGBT chips will be described below, referring toFIG. 7. FIG. 7(a) is a plan view showing the surface of the ceramicsubstrate where the IGBT chips are bonded, that is, where theaforementioned electrode terminals are connected. In FIG. 2, two ceramicsubstrates are illustrated, but one of the two is illustrated in thisfigure. That is, the other side of the substrate is also formedsymmetrically. However, even if it is asymmetric, the basic idea of thepresent invention does not change. The reference character 201 is an AlNceramic substrate bonded with Cu thin plate patterns on the bothsurfaces, the reference character 202 is a collector electrode Cu thinplate pattern, the reference character 204 is a Cu thin plate patternfor short-circuiting upper and lower collector electrode zones, thereference character 203 is an emitter pattern formed by a Cu thin plate,the reference characters 701 a, 701 b are gate patterns formed by Cuthin plates, the reference characters 702 a, 702 b, 702 c, 702 d are theIGBT chips, the reference characters 703 a, 703 b are diode chipsconnected to the IGBT chip in parallel for allowing current to flow inthe opposite direction when the IGBT chip is in OFF state, the referencecharacters 704 a, 704 b, 704 c, 704 d are inner gate resistors which arenot connected in some cases. The reference characters 705 a, 705 bindicate collector terminal connecting positions where the collectorelectrode terminals are connected. These are corresponding to the 205c/205 b and 205 a/205 d in FIG. 2. The reference characters 706 a, 706 bindicate emitter terminal connecting positions where the emitterelectrode terminals are connected. These are corresponding to 207 a and207 b in FIG. 2 (in FIG. 2, terminals are omitted). The referencecharacter 707 is an emitter auxiliary terminal position for extractemitter voltage, and the reference characters 708 a, 708 b are gateterminal connecting positions connected with the gate electrodeterminals. In FIG. 2, the electrode terminals corresponding to 707, 708are omitted.

[0113]FIG. 7(b) shows the equivalent circuit. Since each of thereference characters is corresponding to each of FIG. 7 (a), explanationis omitted. Since in the semiconductor device in FIG. 2 the circuit ofFIG. 7(b) is further connected in parallel, it can be understood thateight IGBT chips and four diode chips are connected in parallel. It isnot always required that the semiconductor device has the same number ofchips, but the number of chips can be varied depending on the currentcapacity of the device. When the semiconductor device is seen as a blackbox, the semiconductor device in the embodiment can be considered to bea single IGBT element connected with a diode in parallel. All the IGBTelements are turned ON/OFF at a time. The diode elements are turnedOFF/ON in the inverse operation of the IGBT. That is, the IGBT elementand the diode element basically does not generate heat at a time.Therefore, it is necessary that the IGBT chips among themselves and thediode chips themselves are arranged dispersedly as much as possible toprevent concentration of heat generation. Although this idea is veryimportant when the thermal conductivities of the substrate and the heatdissipating plate are small, it is also effective when the thermalconductivity of the heat dissipating plate is as large as Cu. On theother hand, it is no need to separate the IGBT chip and the diode chip.In order to perform parallel operation of the IGBT chips uniformly, itis important that there is no time difference in emitter-gate voltageamong chips. The key point is that the inductance of the emitter circuitis suppressed as low as possible. From this idea, in the presentinvention leads the lay-out shown in FIG. 7.

[0114] (1) The four IGBT chips are arranged in two chips in each zone.

[0115] (2) The two collector zones are short-circuited by the conductor204 to make the currents in the two collector zone uniform.

[0116] (3) The IGBT chips in each zone are arranged unevenly and apartfrom each other.

[0117] (4) The IGBT chip and the diode chip are adjacently arranged.

[0118] (5) The emitter pattern is arranged in the center portion of thesubstrate to shorten the emitter wiring in order to lessen itsinductance.

[0119] (6) The emitter terminal connecting positions 706 a, 706 b arearranged near the center of the emitter pattern 203 to protect theceramic under the terminal from cracking with so-called sucking disceffect.

[0120] (7) The distance between the edge of the Cu pattern and the edgeof the ceramic substrate in the side facing to the other substrate(right hand side in the figure) is formed larger than that in the othersides. The reason is that since the solder in the side facing to theother substrate is apt to swell, the distance becomes short.

[0121] Embodiments of semiconductor modules according to the presentinvention will be described below.

[0122] Firstly, the first embodiment of a semiconductor module accordingto the present invention will be described, referring to FIG. 18 to FIG.24. The semiconductor module of this embodiment mounts three diodeelements 101, 102, 103 of same kind and same size as shown in FIG. 18.Each of the diode elements 101, 102, 103 is square-plate-shaped, and onthe top surface of the diode element there is an anode electrode (inputelectrode) through which current flows in from the external, and on thebottom surface there is a cathode electrode (output electrode) throughwhich current floes out to the external.

[0123] The semiconductor module comprises, as shown in FIG. 18 to FIG.20, the three diodes 101, 102, 103 as described above, a metallicsupporting board 114, a rectangular insulator substrate 106 provided onthe supporting board 114, an anode side conductor pattern 105electrically connected to the anode electrodes on the top surfaces ofthe diode elements 101, 102, 103 in parallel, a cathode side conductorpattern 104 electrically connected to the cathode electrodes on thebottom surfaces of the diode elements 101, 102, 103 in parallel, ananode side connecting terminal 109 forming a connecting terminal for anexternal apparatus by being connected to the anode side conductorpattern 105, a cathode side connecting terminal 107 forming a connectingterminal for an external apparatus by being connected to the cathodeside conductor pattern 104, cases 508, 509 coating the diode elementsand so on, and silicone gel 512 shielded in the inner space formed bythe supporting board 114 and the cases 508, 509.

[0124] For the sake of convenience of explanation, here let thedirection parallel to the longer side of the rectangular insulatorsubstrate 106 be X-direction, and the direction perpendicular to theX-direction be Y-direction.

[0125] The anode side conductor pattern 105 and the cathode sideconductor pattern 104 are, as shown in FIG. 21, formed on the insulatorsubstrate 106 so as to become symmetrical in regard to the center line116 (parallel to the Y-direction) of the rectangular insulator substrate106. The anode side conductor pattern 105 is formed in extending in theX-direction in the +Y side of the insulator substrate 106, andprojecting toward the −Y-direction at a portion near the center line116. A portion on the center line 116 in the +Y side of the anode sideconductor pattern 105 is a bonding zone 123 for the anode sideconnecting terminal 109. The cathode side conductor pattern 104 isformed in extending in the X-direction in the −Y side of the insulatorsubstrate 106, and depressing in the −Y-direction at a portion near thecenter line 116. The end portion in the +X side and the end portion inthe −X side in the −Y side of the cathode side conductor pattern 104 arebonding zones 121, 122 of the cathode side connecting terminal 107. Theend portion in the +X side and the end portion in the −X side in the +Yside of the cathode side conductor pattern 104 are mounting zones forthe first and third diode elements 101, 103, and a portion on the centerline 116 in the −Y side of the cathode side conductor pattern 104 is amounting zone for the second diode element 102. The cathode sideconductor pattern 104 between the mounting zone for the first diodeelement 101 and the first bonding zone 121 for the cathode sideconnecting terminal 107 is cut away to form a slit 112. Similarly, thecathode side conductor pattern 104 between the mounting zone for thethird diode element 103 and the second bonding zone 122 for the cathodeside connecting terminal 107 is also cut away to form a slit 112.Further, the anode side conductor pattern 105 between the mounting zonefor the second diode element 102 and the second bonding zone 123 for theanode side connecting terminal 109 is also cut away to form a slit 113.

[0126] The anode side connecting terminal 109, as shown in FIG. 18,comprises a bonding portion 109 a bonded to the bonding zone 123 of theanode side conductor pattern 104, a rising portion 109 b verticallyrising from the bonding portion 109 a, an inducing portion 109 cextending in the −Y-direction from the top of the rising portion 109 b,a facing portion 109 d vertically rising from the −Y side end of theinducing portion 109 c, and a bolt fixing portion 110 extending towardthe +Y-direction from the top end of the facing portion 109 d. A bolt isattached to the bolt fixing portion 110, and a lead wire from anexternal apparatus is fixed to this portion. The cathode side externalconnecting terminal 107 comprises a first bonding portion 107 a bondedto the first bonding zone 121 of the cathode side conductor pattern 104,a second bonding portion 107 a′ bonded to the second bonding zone 122 ofthe cathode side conductor pattern 104, rising portions 107 b, 107 b′vertically rising from the bonding portions 107 a, 107 a′ respectively,an inducing portion 107 c approaching toward the center line 116 fromthe top ends of the rising portions 107 b, 107 b′ respectively, a facingportion 107 d vertically rising from the center of the inducing portion107 c, that is, on the center line 116, and a bolt fixing portion 108extending toward the −Y-direction from the top end of the facing portion107 d. A bolt is attached to the bolt fixing portion 108, and a leadwire from an external apparatus is fixed to this portion.

[0127] The effects of the embodiment due to each of the conductorpatterns 104, 105 and the shapes of the external connecting terminals107. 109 will be described here, referring to FIG. 21 to FIG. 23.

[0128] In this embodiment, as described above referring to FIG. 21,there are formed the slits 112, 112, 113 between the mounting zone ofthe first diode 101 and the first bonding zone 121 of the cathode sideconnecting terminal 107, between the mounting zone of the third diode103 and the second bonding zone 122 of the cathode side connectingterminal 107, and between the mounting zone of the second diode 102 andthe bonding zone 123 of the anode side connecting terminal 109. In thesecond diode 102, the average distance from the anode electrode to thebonding zone 123 of the anode side connecting terminal 109 is shorterthan those of the other semiconductor elements 101, 103. Here, thereason using the term “average distance” is that the anode electrode hasa certain expansion. Therefore, among the current paths between thebonding zone 123 of the anode side connecting terminal 109 and each ofthe semiconductor elements 101, 102, 103, the current path to the seconddiode 102 usually becomes the shortest. Therefore, the current flowingbetween the mounting zone of the second diode 102 and the bonding zone123 of the anode side connecting terminal 109 is bypassed to make eachof the current paths for the plural semiconductor elements 101, 102, 103nearly an equal length. For doing so, a part of the path is cut away toform a current bypass portion 105 a. The current bypass portion 105 a isconnected with one end of a metallic wire 111 which is connected to theanode electrode of the second diode 102. In the first diode 101 and thethird diode 103, the average distances from the cathode electrode to thebonding zones 121, 122 of the cathode side connecting terminal 107 areshorter than that of the other semiconductor element 102. Therefore, thecurrent flowing between the mounting zones of the first and third diodes101, 103 and the bonding zones 121, 122 of the cathode side connectingterminal 107 are bypassed to make each of the current paths for theplural semiconductor elements 101, 102, 103 nearly an equal length. Fordoing so, a part of the paths are cut away to form current bypassportion 104 a, 104 b.

[0129]FIG. 22 a view showing the current paths from the diode elements101, 102, 103 to the bonding zones 121, 122, 123 of the externalconnecting terminals 107, 109 In the cathode side, the length (K1) ofthe current path 131 from the first diode element 101 to the firstbonding zone 121 of the cathode side connecting terminal 107 and thelength (K2) of the current path 132 from the second diode element 102 tothe first bonding zone 121 of the cathode side connecting terminal 107are nearly equal (K1=K2). Since the pattern is symmetrical, the length(K3) of the current path 133 from the third diode element 103 to thesecond bonding zone 122 of the cathode side connecting terminal 107 andthe length (K2) of the current path 134 from the second diode element102 to the second bonding zone 122 of the cathode side connectingterminal 107 are nearly equal (K2=K3). In the anode side, the length(A1) of the current path 131 from the first diode element 101 to thebonding zone 123 of the anode side connecting terminal 109 and thelength (A2) of the current path 136 from the second diode element 102 tothe bonding zone 123 of the anode side connecting terminal 109 arenearly equal (A1=A2). Since the pattern is symmetrical, the length (Al)of the current path 137 from the third diode element 103 to the bondingzone 123 of the anode side connecting terminal 109 and the length (A2)of the current path 138 from the second diode element 102 to the bondingzone 123 of the anode side connecting terminal 109 are nearly equal(A1=A2), Therefore, all the inductances between the semiconductorelements 101, 102, 103 and the bonding zone 121, 122, 123 of theexternal connecting terminals 107, 109 are nearly equal to one another,and accordingly the current flowing to each of the elements can be madeequal. As the result, the spike noise during operation of a diode modulecan be decreased, and the heat generating rates of the elements can beuniform. Therefore, the reliability in the solder 505 and metallic wire111 bonding each of the elements can be improved.

[0130] Each of the elements has each anode electrode having a certainexpansion. Therefore, even if the length of the current path 131 from acertain position in the anode electrode of the first diode element 101to the bonding zone 123 of the anode side connecting terminal 109 andthe length of the current path 136 from a certain position in the anodeelectrode of the second diode element 102 to the bonding zone 123 of theanode side connecting terminal 109 are made equal to each other, thelength of the current path 131 from another position in the anodeelectrode of the first diode element 101 to the bonding zone 123 of theanode side connecting terminal 109 and the length of the current path136 from a certain position in the anode electrode of the second diodeelement 102 to the bonding zone 123 of the anode side connectingterminal 109 are not exactly equal. In the embodiment, the meaning “tomake the length of each of the current paths nearly equal to each other”is that the difference in lengths of the shortest current path in eachsemiconductor elements is shorter than one half of one side-length ofthe semiconductor element. The semiconductor element in the embodimentis square plate-shaped. In a case of rectangular plate-shaped elements,the meaning “to make the length of each of the current paths nearlyequal to each other” is that the difference is shorter than one half ofthe length of the longer or shorter side of the element along which thecurrent path crosses. In a case of cylinder elements, the meaning isthat the difference is shorter than one half of the diameter of theelement.

[0131] Since the conductor patterns 104, 105 on the insulator substrate106 play a role in improving the cooling effect by dissipating heatgenerated in the diode elements, it is preferable to lessen the sizes ofthe slits 112, 113 as small as possible. Therefore, as shown in FIG. 21,the position of the second diode element 102 in the center is shiftedtoward the −Y direction from the other diode elements 101, 103 so thatthe centers of weight of the diode elements 101, 102, 103 does not comeon a straight line. The second diode element 102 is moved close to thebonding zones 121, 122 and away from the bonding zone 123 to shorten thelength of the slits 112, 113. By shifting the second diode element 102from the other diode elements 101, 103, the heat generating positionscan be dispersed. It is necessary to design the slits 112, 113 in takingthe current density in the conductor pattern into consideration so thatthe conductor pattern itself generates much heat by extreme currentconcentration. In this case, the current density is preferablysuppressed 100 A/mm² at maximum as a target although it depends on thecooling effect of the module. By arranging the slits 112, 113 near thebonding zones 121, 122, 123 of the external connecting terminals 107,109, it is possible to suppress the solder 505 bonding the externalconnecting terminal 107, 109 and the conductor pattern 104, 105 to flow,and it is easy to position the terminals at assembling the module byutilizing the slits 112,113 as positioning marks. As described above, bysuppressing the solder 505 to flow, the thickness of the solder 505 usedfor connection of terminals can be made uniform, and degradation of thesolder by thermal cycle during operation can be decreased, and furtherthe size if the module can be decreased by decreasing the marginal areaagainst flowing of solder.

[0132]FIG. 23 shows a case where number of diode elements in a module ischanged. In a case of one diode element or two diode elements, as shownin FIGS. 23(b), (d), it is possible to make the current path lengthsfrom the anode electrode or the cathode electrode of each element to thebonding zone of the external connecting terminal nearly equal only bymaking the shape of each conductor pattern, the arrangement of eachelement and arrangement of bonding zones of the external connectingterminals symmetrical without forming slit in the conductor pattern. Inother words, in the case of FIG. 23(b), the relation K1−1(158)=K1−2(159)can be obtained. In the case of FIG. 23 (d), the relationsA−1(160)=A−2(161) and K−1(162)=K−2(163) can be obtained. However in acase of three semiconductor elements, it is impossible to make thecurrent path lengths from the anode electrode or the cathode electrodeof each element to the bonding zone of the external connecting terminalnearly equal without slits in the conductor pattern. By making the shapeof each conductor pattern symmetrical and forming the silts in theconductor pattern as in the embodiment, it is possible to make thecurrent path lengths from the anode electrode or the cathode electrodeof each element to the bonding zone of the external connecting terminalnearly equal in any case of one diode element, two diode elements andthree diode elements as shown in FIGS. 23(a), (b), (c). In other words,in the case of FIG. 23(a), the relations A−1(141)=A−2(142) andK−1(143)=K−2(144) can be obtained. In, the case of FIG. 23(c), therelations A−1(145)=A−2(146) and K−1(147)=K−2(148) can be obtained In thecase of FIG. 23 (e), the relations A−1(149)=A2−1(151)=A2−2(152)=A−3(150)and K−1(153)=K2−1(154)=K2−2(156)=K−3(155) can be obtained.

[0133] By making the shape of each conductor pattern symmetrical andforming the silts in the conductor pattern as in the embodiment, it ispossible to cope with various number of semiconductors and to improvethe versatility of module.

[0134] In the embodiment, the arrangement of the diode elements 101,102, 103, the shape of the conductor patterns 104, 105, the shape of theexternal connecting terminals 107, 109 and the arrangement of bondingzones 121, 122, 123 of the external connecting terminals 107, 109symmetrical without forming slit in the conductor pattern aresymmetrical in regard to the center line 116 of the insulator substrate106. Basically, in order to make the inductance of each element equal,it is possible to design the slits 112, 113 properly. However, it isvery complex to design the slits 112, 113 for making the inductancesequal unless the shape of the conductor patterns 112, 113 and the likeare symmetrical. Further, as described above referring to FIG. 23, thedegree of freedom in regard to number of semiconductor elements and thelayout of the semiconductor elements is decreased. Therefore, in theembodiment, the shape of the conductor patterns 112, 113 and the likeare symmetrical in order to easily design for making the inductance toeach element equal and to increase the degree of freedom in regard tonumber of semiconductor elements and the layout of the semiconductorelements.

[0135] In general, an inductance L of each of two parallel wires isgiven by the following equation.

L=4×1·ln(D/r)  (Equation 2)

[0136] where 1 is length of the wire, D is distance between the wires,and r is radius of the wire.

[0137] When the currents in the parallel wires are flowing in the samedirection, the self-inductances are mutually increased. When thecurrents in the parallel wires are flowing in the opposite directions,the self-inductances are mutually canceled. In the case where thecurrents in the parallel wires are flowing in the opposite directions,the mutual inductance is rapidly decreased when the distance between thewires D becomes below 10 mm as shown in FIG. 24.

[0138] In the embodiment, as shown in FIG. 19, the facing portion 109 dof the anode side connecting terminal 109 and the facing portion 107 dof the cathode side connecting terminal 107 are parallel to and facingto each other, and the gap between them is less than 10 mm. Further, thedirections of the currents flowing in the facing portion 109 d of theanode side connecting terminal 109 and in the facing portion 107 d ofthe cathode side connecting terminal 107 are opposite. Therefore, theinductance in the module can be substantially decreased. Incidentally,in the embodiment, since the width of the facing portion 107 d, 109 d ofthe external connecting terminals 107, 109, that is, the radius of wireis 3 mm. The calculation of the inductance in FIG. 24 is performed basedon wire length 1 of 10 mm and wire radius of 3 mm to meet with thecondition of the embodiment.

[0139] The second embodiment of a semiconductor module according to thepresent invention will be described below, referring to FIG. 25 and FIG.26.

[0140] The semiconductor module in this embodiment comprises two sets ofinsulator substrates each of which mounts three IGBT elements and onediode element as shown in FIG. 25. The IGBT element is squareplate-shaped, having an emitter electrode (input electrode) and a gateelectrode (control electrode) on the top surface, and a collectorelectrode (output electrode) on the bottom surface.

[0141] On a metallic supporting board 114, two insulator substrates 106,106 made of aluminum nitride are arranged symmetrically in regard to thecenter line 622 of the metallic supporting board 114. On one of theinsulator substrate 106, conductor patterns 610, 611, 614 made of copperare formed. Among the conductor patterns 610, 611, 614, on the collectorside conductor pattern 610, the IGBT elements 601, 602, 603 and thediode element 607 are arranged and a collector side connecting terminal612 is bonded. The collector side connecting terminal 612 has two legsone of which is bonded to the collector side conductor pattern 610 onone of the insulator substrates 106. On the gate side conductor pattern611, three gate resistor elements 609 are arranged and a gate sideconnecting terminal 620 is bonded. The gate side connecting terminal 620also has two legs one of which is bonded to the gate side conductorpattern 611 on one of the insulator substrates 106. On the emitter sidepattern 614, a slit 615 is formed and an emitter side connectingterminal 616 and an emitter auxiliary connecting terminal 618 arebonded. The emitter side connecting terminal 616 also has two legs oneof which is bonded to the emitter side conductor pattern 614 on the oneof the insulator substrates 106. An anode electrode formed on the topsurface of the diode element 607 and the emitter side conductor pattern614 are connected by a metallic wire 111. Emitter electrode formed onthe top surfaces of the IGBT elements 601, 602, 602 and the emitter sideconductor pattern 614, gate electrodes formed on the top surfaces of theIGBT elements 601, 602, 603 and the gate resistor element 609 on thegate side conductor pattern 611 are also connected with the metallicwires 111. In FIG. 25, the reference character 115 is casing couplinghole, the reference character 613 is a bolt fixing portion of thecollector side terminal, the reference character 617 is a bolt fixingportion of the emitter side connecting terminal, the reference character619 is a bolt fixing portion of the emitter auxiliary connectingterminal, and the reference character 621 is a bolt fixing portion ofthe gate side connecting terminal.

[0142] As shown in FIG. 26, the shape of each semiconductor element(excluding the portion in relation to the diode element 607), thearrangement of each of the IGBT elements 601, 602, 603, the arrangementof each of the gate resistor element 609, the arrangement of the bondingzone 719 of the emitter side connecting terminal 616 and the like aresymmetrical in regard to a specified line (a line parallel to the Xdirection) 622 a on the insulator substrate 106, and the silt 615 isprovided. Therefore, the lengths of the current paths 711, 712, 714, 713between the emitter electrodes of the IGBT elements 601, 602, 603 andthe bonding zone 719 of the emitter connecting terminal 616 can be madeequal. That is, E−1=E−2−1=E−2−2=E−3. Here, by forming the slit 615 inregard to the Y direction from a position of the midpoint of the gapbetween the first IGBT element 601 and the second IGBT element 602 inthe Y direction to a position of the midpoint of the gap between thesecond IGBT element 602 and the third IGBT element 603 in the Ydirection, the lengths of the current paths 711, 712, 713, 714 betweenthe emitter electrodes of the IGBT elements 601, 602, 603 and thebonding zone 719 of the emitter side connecting terminal 616 can be madeequal.

[0143] Although the above is description on one of the insulatorsubstrates 106. In the embodiment, the arrangement and the shape on theother of the insulator substrates 106, the arrangement of each of theelements 604, 605, 606, 608, 609 on the other of the insulatorsubstrates 106, the shapes of the conductor patterns 610, 611, 614, theshape of each of the external connecting terminals 612, 616, 618, 620,the arrangement of the bonding zones 720, 722, 724 of each of theexternal connecting terminals 612, 616, 618, 620 on the other of theinsulator substrates 106 are made symmetrical to one of the insulatorsubstrates 106 and these provided on one of the insulator substrate.Therefore, the same amount of current can be conducted to the elementson one of the insulator substrate 106 and the elements on the other ofthe insulator substrates 106.

[0144] The third embodiment of a semiconductor module according to thepresent invention will be described below, referring to FIG. 27 and FIG.28. The different points of this embodiment from the second embodimentare that only two IGBT elements 601, 602 are mounted on one insulatorsubstrate 106, there is no slit on the conductor pattern, and the shapeof each of the external connecting terminals and the arrangement of thebonding zone of each of the external connecting terminals are different.The others are basically the same as in the second embodiment.Therefore, the different points from the second embodiment will bedescribed in detail below.

[0145] The collector side connecting terminal 612 comprises bondingportions 612 a, 612 a′ bonded to the collector side conductor patterns610, 610 symmetrical in regard to the center line 622 of the metallicsupporting board 114, first rising portions vertically rising from thebonding portions 612 a, 612 a′, first inducing portions extending fromthe top ends of the first rising portions in the direction away from thecenter line 622, second rising portions vertically rising from the endsof the first inducing portions, a second inducing portion 612 bextending from the top ends of the second rising portions in thedirection approaching to the center line 622, a facing portion 612 cvertically rising from the middle of the second inducing portion 612 b,that is, from a position on the center line 622, and a bolt fixingportion 613 extending from the top end of the facing portion 612 c inthe +Y direction.

[0146] The emitter side connecting terminal 616, as shown in FIG. 27 andFIG. 28, comprises bonding portions 616 a, 616 a′ bonded to emitter sideconductor patterns 614, 614 symmetrical in regard to the center line 622of the metallic supporting board 114 using a solder 505, first risingportions 616 b, 616 b′ vertically rising from the bonding portions 616a, 616 a′, first inducing portion 616 c, 616 c′ extending from the topdens of the first rising portions 616 b, 616 b′ in the −Y direction,second rising portions 616 d, 616 d′ vertically rising from the −Y sideend of the first inducing portions 616 c, 616 c′, second inducingportions 616 e, 616 e′ extending from the top ends of the second risingportion 616 d, 616 d′, a third inducing portion 612 f extending from thesecond inducing portions 616 e, 616 e′ approaching to the center line622, a facing portion 616 g vertically rising from the middle of thethird inducing portion 612 f, that is, from a position on the centerline 622, and a bolt fixing portion 617 extending from the top end ofthe facing portion 616 g in the −Y direction.

[0147] The bonding portions 616 a, 616 a′ of the emitter side connectingterminal 616 are bonded to positions on the emitter side conductorpatterns 614, 614 and as close to the diode elements 607, 608 aspossible. The emitter side connecting terminal 616 serves the diodeelements 607, 608 as an anode side connecting terminal. When the bondingportions 616 a, 616 a′ is close to the diode elements 607, 608, theinductances between the bonding portions 616 a, 616 a′ and the diodeelements 607, 608 can be lessened. As the result, even if the currentfluctuation dI/dt during switching operation is large, the current overshoot is small and the noise current due to current oscillation to thegate electrode can be decreased.

[0148] The first inducing portions 616 c, 616 c′ and the second inducingportions 616 e, 616 e′ of the emitter side connecting terminal 616 areparallel to and facing to the patterns 614, 614. Further, the firstinducing portions 616 c, 616 c′ and the second inducing portions 616 e,616 e′ are extended from the position of the IGBT element 604 to theposition of the IGBT element 605 in the Y direction. As described above,when currents flow in the opposite direction in parallel wires, theinductance in the parallel wires can be cancelled. In this embodiment,the current 1005 flowing in the emitter side conductor patterns 614, 614and the current 1007 flowing in the second inducing portions 616 e, 616e′ are in the opposite direction to the current 1006 flowing in thefirst inducing portions 616 c, 616 c′. Consequently, the inductances ofthe first inducing portions 616 c, 616 c′, the second inducing portions616 e, 616 e′ and the emitter side conductor patterns 614, 614 arecancelled. Therefore, the Y direction component of the differencebetween the current path from the IGBT element 604 to the bondingportion 616 a′ of the emitter side connection terminal 616 and thecurrent path from the IGBT element 605 to the bonding portion 616 a′ ofthe emitter side connecting terminal 616 is cancelled. On the otherhand, as for the X direction, there is no difference between the currentpath from the IGBT element 604 to the bonding portion 616 a′ of theemitter side connection terminal 616 and the current path from the IGBTelement 605 to the bonding portion 616 a′ of the emitter side connectingterminal 616. Therefore, although there is a difference between thelength of the current path from the IGBT element 604 to the bondingportion 616 a′ of the emitter side connection terminal 616 and thelength of the current path from the IGBT element 605 to the bondingportion 616 a′ of the emitter side connecting terminal 616, thedifference in inductance between both of the current paths can be almosteliminated.

[0149] As described above, independently of the symmetry in element andconductor pattern and the number of elements, it can be easily realizedto eliminate the difference in inductance of the current path for eachelement by forming the facing portion facing to the conductive patternin the external connecting terminal.

[0150] The facing portion 616 g of the emitter side connecting terminal616 and the facing portion 612 c of the collector side connectingterminal 612 are facing to and parallel to each other, and the gap is 10mm. Further, the currents flowing in both of the facing portions areopposite to each other. Therefore, the inductance in this portion iscancelled, and consequently the inductance of the whole module can bedecreased.

[0151] The emitter side connecting terminal 616 has first inducingportions 616 c, 616 c′, second rising portions 616 d, 616 d′ and abonded portion 1004 formed by the second inducing portions 616 e, 616e′. Therefore, it is possible to absorb the difference of thermalexpansion of the casing (not shown) and the external connectingterminals 612, 616 similar to the first embodiment.

[0152] In this embodiment, each of the external connecting terminals isarranged without crossing with the other external connecting terminalinside the module. Therefore, noise during switching operation can bedecreased.

[0153] In general, the control current (or control voltage) flowing inthe gate side connecting terminal 620 is easily affected by noise suchas electromagnetic induction from the gate side connecting terminal 620and the collector side connecting terminal 612. Therefore, in theembodiment of a semiconductor module according to the present invention,the gate side connecting terminal 620 is arranged in the −Y side on theinsulator substrate 106, and the collector side connecting terminal 612and the emitter side connecting terminal 616 are arranged in the +Y sideon the insulator substrate 106. By doing so, the gate side connectingterminal 620 is separated from the collector side connecting terminal612 and the emitter side connecting terminal 616 to prevent the noisefrom entering the control current.

[0154] The fourth embodiment and the fifth embodiment of semiconductormodules according to the present invention will be described below,referring to FIG. 29 and FIG. 30 respectively.

[0155] The fourth embodiment of a semiconductor module is an IGBT modulemounting two IGBT elements 601, 603 and one diode element 607 as shownin FIG. 29. On a metallic supporting board 114, an insulator substrate106 is arranged by putting its center on the center line 622. On theinsulator substrate 106, a collector side conductor pattern 610, anemitter side conductor pattern 614 and a gate side conductor pattern 611are formed so that the positions and the shapes are symmetrical inregard to the center line 622. On the collector side conductor pattern610, the IGBT elements 601, 603 and the diode element 607 are arrangedand a collector side connecting terminal 612 is bonded. On the gate sideconductor pattern 611, two gate resistor elements 609, 609 are arrangedand a gate side terminal 620 is bonded. On the emitter side conductorpattern 614, an emitter side connecting terminal 616 and an emitterauxiliary connecting terminal 618 are bonded. The emitter auxiliaryconnecting terminal 618 has a leg common to the leg of the emitter sideconnecting terminal 616 and its bolt fixing portion 619 is formed bybranching from the middle of the emitter side connecting terminal 616.The emitter electrodes formed on the top surfaces of the IGBT elements601, 603 and the emitter side conductor pattern 614, the gate electrodesformed on the top surfaces of the IGBT elements 601, 603, the gateelectrodes formed on the top surfaces of the IGBT elements 601, 603 areconnected with metallic wires 111 respectively.

[0156] In a case where number of bonding positions between the conductorpattern and the external connecting terminals 612, 616, 620 is three asdescribed above, in the assembling process of attaching a terminalblock, which is integrated with the external connecting terminals and acasing cover, to the metallic supporting board 114, it is possible thatall the external terminals certainly contact to the respective bondingpositions even if there are errors in the level of the terminal bondingportions when the external connecting terminals are bonded to theinsulator substrate 601 provided on the metallic supporting board 114using solder. Therefore, contact defect of terminal does not occur.Further, the thickness of solder can be made uniform.

[0157] Since the diode element 607 is placed on the center line 622, thedistance to the bonding zone of the emitter side connecting terminal(input side connecting terminal) 616 also placed on the center line 622is shorter than that of the IGBT elements 601, 602. In more detail, thebonding zone of the emitter side connecting terminal 616 is in aposition where the current path length from the position to the anodeelectrode (input electrode) of the diode element 607 is shorter than thecurrent path length from the position to the emitter electrodes (inputelectrodes) of the IGBT elements 601, 602. Therefore, since the bondingzone of the emitter side connecting terminal 616 is close to the diodeelement 607, the inductance of the current path from the position to theanode electrode of the diode element 607 becomes small. As the result,as described above, even if the current fluctuation dI/dt duringswitching operation is large, the current over shoot is small and thenoise current due to current oscillation to the gate electrode can bedecreased.

[0158] The fifth embodiment of a semiconductor module is a diode modulemounting two diode elements 101, 102 as shown in FIG. 30. On a metallicsupporting board 114, an insulator substrate 106 is arranged by puttingits center on the center line 116. On the insulator substrate 106, acathode side conductor pattern 104, an anode side conductor pattern 105so that the positions and the shapes are symmetrical in regard to thecenter line 116. In the cathode side conductor pattern 104, slits 112,112 are formed, and two diode elements 101, 102, a cathode sideconductor terminal 107 and an auxiliary support column 1201 are bonded.The two diode elements 101, 102 are arranged symmetrically in regard tothe center line 116. The two slits 112,112 are also formed symmetricallyin regard to the center line 116. The cathode side connecting terminalis arranged on the center line 116. In the anode side conductor pattern105, a slit 113 is formed and an anode side connecting terminal isbonded. The slit 113 is formed symmetrically in regard to the centerline 116. The anode side connecting terminal 109 is arranged on thecenter line 116. Anode terminals formed on the top surfaces of the diodeelements 101, 102 and the anode side conductor pattern 105 are connectedwith metallic wires 111.

[0159] In a case where there are not three external connecting terminalsas this case, by providing the auxiliary column 1201 which does not playany electrical role, the same effect as in the fourth embodiment can beattained.

[0160] In the fourth and the fifth embodiments, number of columns(including external connecting terminals) is three. In a case wherenumber of parallel elements in a module is increased in order toincrease electrical capacity of module, four or more columns may beprovided. However, in this case, it is important to align the level ofthe columns accurately in its assembling process.

[0161] In the above embodiments, IGBT elements and external connectingterminals are arranged symmetrically in regard to a certain phantomline. However, it is acceptable that only most important portions formatching inductance to each IGBT, that is, the emitter side connectingterminal (input side connecting terminal) 616 and the collector sideterminal (output side terminal) 612, in which main current flows, aresymmetrically arranged, and the gate side connecting terminal (controlconnecting terminal) 620 and the emitter auxiliary connecting terminal(control connecting terminal) 618 are arranged not symmetrically. Evenif the gate side connecting terminal 620 and the emitter auxiliaryconnecting terminal 618 are arranged not symmetrically, the currentflowing in each of the elements does not become unbalance. Therefore,when an inverter or something is produced by combining a plurality ofmodule, it is possible to select a most effective configuration forwiring paths without symmetrical arrangement of the gate side connectingterminal 620 and the emitter auxiliary connecting terminal 618. However,since the gate connecting terminal 620 is apt to be affected by noisedue to electromagnetic induction from the main connecting terminal (theemitter side connecting terminal 616 and the collector side connectingterminal 612), it is preferable to arrange the gate connecting terminalaway from the main connecting terminal as far as possible.

[0162] As for matching of inductance to each of IGBT elements and diodeelements, it is not always necessary that the emitter side connectingterminal 616 and the collector side terminal 612, in which main currentflows, are symmetrically arranged. By cutting away a part of theconductor pattern and forming a current bypass portion, or by forming aturn back portion in the external connecting terminal, the inductancematching can be obtained. However, even in this case, the symmetry inthe shape of the conductor pattern is preferable from the stand point ofeasiness of design and degree of freedom on layout of semiconductorelements.

[0163] The sixth embodiment of a semiconductor module will be describedbelow, referring to FIG. 31 to FIG. 33. In the embodiment, the externalconnecting terminals are not arranged symmetrically in regard to acertain phantom line.

[0164] The semiconductor module in this embodiment comprises two sets ofinsulator substrates each of which mounts three IGBT elements and onediode element as shown in FIG. 31. On a metallic supporting board 114,two insulator substrates 106, 106 are arranged symmetrically in regardto the center line 622 of the metallic supporting board 114. On one ofthe insulator substrate 106, conductor patterns 610, 611, 614 areformed. Among the conductor patterns 610, 611, 614, on the collectorside conductor pattern 610, the IGBT elements 601, 602, 603 and thediode element 607 are arranged and a collector side connecting terminal612 is bonded. The collector side connecting terminal 612 has two legsone of which is bonded to the collector side conductor pattern 610 onone of the insulator substrates 106. On the gate side conductor pattern611, three gate resistor elements 609 (not shown) are arranged and agate side connecting terminal 620 is bonded. The gate side connectingterminal 620 also has two legs one of which is bonded to the gate sideconductor pattern 611 on one of the insulator substrates 106. On theemitter side pattern 614, an emitter side connecting terminal 616 and anemitter auxiliary connecting terminal 618 are bonded. The emitter sideconnecting terminal 616 also has two legs one of which is bonded to theemitter side conductor pattern 614. An anode electrode formed on the topsurface of the diode element 607 and the emitter side conductor pattern614, a metallic electrode and the gate resistor element (not shown) onthe gate side conductor pattern 611 are connected by metallic wires 111(not shown), respectively.

[0165] Among the two insulator substrates 106, 106, the conductorpatterns 610, 611, 614 and various elements 604, 605, 606, 608 arearranged on the other substrate 106 symmetrically in regard to those onone insulator substrate 106.

[0166] The collector side connecting pattern 612 comprises, as shown inFIG. 31 and FIG. 32, bonding portions 612 i, 612 i′ bonded to thecollector side conductor pattern 610, 610 symmetrical in regard to thecenter line 622, first rising portions 612 j, 612 j′ vertically risingfrom the bonding portions 612 i, 612 i′, an inducing portion 612kextending from one of the first rising portion 612 j to the other of thefirst rising portion 612 j′, a second rising portion 6121 verticallyrising from the end of the inducing portion 612 k, and a bolt fixingportion 613 extending from the top end of the second rising portion 6121in the +Y direction. That is, in the collector side connecting terminal612, the bonging portions 612 i, 612 i′, although the first risingportions 612 j, 612 j′ and the inducing portion are symmetrical, thesecond rising portion 6121 and the bolt fixing portion 613 are notsymmetrical.

[0167] The inductance component from the diode elements 607, 608 to thebolt fixing portion 613 of the collector side connecting terminal 612is, as shown in FIG. 32 and FIG. 33, composed of an inductance componentL5 from the first diode 607 to the first bonding portion 612 j′ of thecollector side connecting terminal 612, an inductance component L4 fromthe second diode 608 to the second bonding portion 612 l of thecollector side connecting terminal 612, an inductance component L3 fromthe first bonding portion 612 j′ of the collector side connectingterminal 612 to the second rising portion 612 l, an inductance componentL2 from the second bonding portion 612 j of the collector sideconnecting terminal 612 to the second rising portion 612 l, and aninductance component L1 from the second rising portion 612 l of thecollector side connecting terminal 612 to the bolt fixing portion 613.

[0168] In order to keep the inductance matching to each of the diodeelements, it is sufficient to satisfy the relation (L3+L5)=(L2+L4) sincethe component L1 among these inductance components is common to the bothdiode elements 607, 608. If (L3+L5) in the first diode side is largerthan (L2+L4) in the second diode side, a part of the inducing portion612 k is formed to decrease (L3+L5) in the first diode side in such thatthe part of the inducing portion 612 k and the first collector sideconductor pattern 610 are arranged to be parallel to and facing to eachother. On the contrary, it is also possible that in order to increase(L2+L4) in the second diode side, a part of the pattern 610 between thesecond diode 608 and the bonding portion 612 i is cut away to bypass thecurrent.

[0169] Application of a semiconductor device according to the presentinvention to an inverter will be described below, referring to FIG. 8. Athree-level control inverter is taken as an example. FIG. 8 shows amounting feature of IGBT modules (being regarded as a semiconductordevice) for one phase. The Illustration of gate circuit and so on areomitted in the figure. FIG. 9 shows the equivalent circuit (diodes areomitted) In this embodiment, the modules are connected in parallel. Thecomponents for three phase are required to form an inverter. One arm iscomposed of the modules 801 a, 801 b, 802 a, 802 b. The referencecharacters 805 to 809 are bus bars for connecting individual terminals.It can be understood that the inverter is short in vertical length andthe modules are connected with simplified bus bars by arranging themodules so that the shorter side of the module directs to the verticaldirection and the collector terminals and the emitter terminals arealigned in parallel to the direction of the shorter side.

[0170] The main effects of the aforementioned embodiments are asfollows.

[0171] (1) Since the linear expansion coefficients of chip, ceramicsubstrate, metallic base are matched, the life time of the solderbonding these materials is substantially improved.

[0172] (2) A gate resistor required for parallel operation can beconnected so as not to be affected by noise.

[0173] (3) Occurrence of crack in gel can be suppressed. The gel crackoccurs in a convectional manufacturing process.

[0174] (4) Hermeticity inside the device can be improved.

[0175] (5) Injection of a hard resin for keeping the hermeticity can bevisually and easily controlled.

[0176] (6) The device can be fixed without loosing.

[0177] (7) The inductance of terminal can be decreased.

[0178] (8) Thermal resistance can be decreased and heat generated in achip can be dissipated.

[0179] (9) The weight of device can be decreased.

[0180] (10) The mounting area of devices can be decreased and the wiringcan be simplified by arranging the collector and the emitter terminalsso as to align in the direction of the shorter side of the device.

[0181]FIG. 10 shows another embodiment according to the presentinvention. The reference character 11 is a terminal block, the referencecharacter 13 is a base made of Mo, the reference characters 14 b, 14 care hard resin for keeping hermeticity between the terminal and theterminal block, the reference characters 15 a, 15 b are an emitterterminal and a collector terminal respectively, the reference character201 is an AlN ceramic substrate, the reference characters 401 a, 401 bare mold members covering the terminals for keeping the insulationbetween the terminals, and the reference character 901 is an insulatinggroove lengthen the surface distance between the terminals. Thisembodiment has an effect in that the height of the device can be loweredwhile the inductance of terminal is suppressed small.

[0182]FIG. 11 shows a further embodiment according to the presentinvention. In FIG. 11(a), the reference character 13 is a metallic basemade of Mo, the reference character 201 is a ceramic substrate which ispreferably made of a material having a thermal expansion coefficientnear that of Si and a large thermal conductivity. AlN ceramic ispreferable as described above. Alumina may be employed. The referencecharacters 202 and 302 are Cu thin plate patterns attached to bothsurfaces of the ceramic substrate 201, the reference character 301 is aeutectic solder bonding the ceramic substrate 201 and the Mo base 13,and the reference character 1002 is a flat electrode formed inside theceramic substrate and not exposing its end. The flat electrode may be asolid layer or a mesh. This layer is short-circuited to the collectorpattern 202 connected to the collector terminal 205 through a via hole1001. In this embodiment, a high voltage is applied between the terminal205 and the base 13. Even if the collector pattern 202 is separated fromthe AlN ceramic substrate 201, electric field does not applied to theseparated portion. Therefore, the partial discharge does not occur.

[0183]FIG. 11(b) shows change of thermal shear stress on the surface ofthe ceramic substrate just under the collector pattern 202 when thebonding position of the terminal is changed in FIG. 11(a). The stress isschematically illustrated for the purpose of easy understanding.

[0184]FIG. 12 shows another embodiment according to the presentinvention. The reference character 13 is a metallic base made of Mo, thereference character 201 is a ceramic substrate which is preferably madeof a material having a thermal expansion coefficient near that of Si anda large thermal conductivity. AlN ceramic is preferable as describedabove. Alumina may be employed. The reference characters 202 and 302 areCu thin plate patterns attached to both surfaces of the ceramicsubstrate 201, the reference character 301 is a eutectic solder bondingthe ceramic substrate 201 and the Mo base 13, and the referencecharacter 1101 is an intermediate member which is made of a metal havinga linear expansion coefficient near that of the ceramic substrate andpreferably made of Mo. It is preferable that the collector terminal 205and the intermediate member 1101 are welded, but may be soldered. Theintermediate member 1101 and the AlN ceramic substrate 201 are bondedwith a eutectic solder 306 through the collector pattern 202. In thisembodiment, since the both side surfaces of the collector pattern 202are restricted with materials having linear expansion coefficients closeto each other, the collector pattern 202 does not separated from theceramic substrate 201.

[0185]FIG. 13 shows a still further embodiment according to the presentinvention. This figure is drawn base on FIG. 5. Here, only the differentpoint between the both will be described. In this embodiment, the case12 (refer FIG. 5) and the terminal block 11 are integrally formed.Therefore, there is no need to hermetically joint the case 12 and theterminal block 11 using a hard resin as shown in FIG. 5.

[0186] According to the present invention, it is possible to obtain asmall semiconductor device which is long in solder connecting life,small in thermal resistance and hard to cause deterioration inwithstanding voltage.

What is claimed is:
 1. A semiconductor device in which a plurality ofsemiconductor elements are bonded onto at least one electrode pattern onan insulator substrate formed a plurality of electrode patterns on themain surface, each of the electrodes of said semiconductor element beingelectrically connected to said electrode pattern, the other surface ofthe insulator substrate being bonded to a heat dissipating base, theupper surface of said heat dissipating base being covered with a memberfor cutting off said semiconductor elements from the outer environment,terminals electrically connecting the electrodes on said insulatorsubstrate and the electrode placed outside said cutoff member beingprovided, wherein the material of said heat dissipating base has alinear expanding coefficient larger than the linear expansioncoefficient of the semiconductor element and smaller than three times ofthe linear expansion coefficient of the semiconductor element, and athermal conductivity larger than 100 W/mK; said semiconductor elementsbeing arranged on at least one electrode surface and in at least tworegions divided by the other electrode surface on said insulatorsubstrate.
 2. A semiconductor device according to claim 1, wherein saidplurality of semiconductor elements, the main surface of said insulatorsubstrate and the upper surface of said heat dissipating base are coatedwith a gelatin, the surface of said gelatin being substantially exposedto a space inside said cutoff member.
 3. A semiconductor deviceaccording to claim 1, wherein a space is provided between the electrodepattern portion connected with said electrode terminals on the insulatorsubstrate and said insulator substrate, a metallic patter being formedon the side of the insulator substrate so as to include the projectingarea of said space to said insulator substrate, said metallic patternbeing in the same electrical potential as said electrode pattern.
 4. Asemiconductor device according to claim 1, wherein said insulatorsubstrate comprises on the substrate at least one inter-layer electrodepattern without exposing the end surface having the same electricalpotential as the main current electrode pattern formed on the mainsurface of the substrate.
 5. A semiconductor device according to claim1, wherein an interposing member having a linear expansion coefficientnear the linear expansion coefficient of the heat dissipating base isinserted between the main current electrode and the electrode on theinsulator substrate corresponding to the main current electrode.
 6. Asemiconductor device according to claim 1, wherein in at least one ofthe terminals the distance between the end of the terminal connectedwith said electrode terminal and the end of the electrode pattern on theinsulator substrate corresponding to said terminal is substantiallylarger than twice of the sum of the thickness of the member constructingthe terminal and the thickness of said electrode pattern.
 7. Asemiconductor device according to claim 1, wherein the main externalelectrodes are arranged parallel to the direction of the shorter side ofthe semiconductor device.
 8. A semiconductor device according to claim1, wherein a collar made of a material having a linear expansioncoefficient substantially equal to the linear expansion coefficient ofthe fixing bolt for attaching said device to an external cooling plateis attached to a hole for attaching said device to the external coolingplate.
 9. A semiconductor device according to claim 1, wherein two ofthe main current terminals are arranged within the gelatin in crossingto each other and spacing in the height direction, the raising portionsfrom the inside of the gelatin to the external electrodes being inparallel to each other.
 10. A semiconductor device according to claim 1,wherein an auxiliary terminal for connecting a resistor is provided inthe input terminal.
 11. A semiconductor device according to claim 2,wherein the terminals in the space above the surface of said gelatin arecovered with a material equivalent to the material making said cutoffmember.
 12. A semiconductor device according to claim 2, wherein themembers composing said terminals and another of said cutoff member arebonded with a hard resin.
 13. A semiconductor device according to claim2, wherein said cutoff member and the terminals are molded as a unit orbonded with a hard resin.
 14. A semiconductor device in which aplurality of semiconductor elements are bonded onto at least oneelectrode pattern on an insulator substrate formed a plurality ofelectrode patterns on the main surface, each of the electrodes of saidsemiconductor element being electrically connected to said electrodepattern, the other surface of the insulator substrate being bonded to aheat dissipating base, the upper surface of said heat dissipating basebeing covered with a member for cutting off said semiconductor elementsfrom the outer environment, terminals electrically connecting theelectrodes on said insulator substrate and the electrode placed outsidesaid cutoff member being provided, wherein said semiconductor elementsare arranged on at least one electrode surface and in at least tworegions divided by the other electrode surface on said insulatorsubstrate, at least the semiconductor elements, the main surface of saidinsulator substrate and the surface of the heat dissipating base beingcoated with a gelatin, the surface of said gelatin being substantiallyexposed to a space inside said cutoff member.
 15. A semiconductor deviceaccording to claim 14, wherein a space is provided between the electrodepattern portion connected with said electrode terminals on the insulatorsubstrate and said insulator substrate, a metallic patter being formedon the side of the insulator substrate so as to include the projectingarea of said space to said insulator substrate, said metallic patternbeing in the same electrical potential as said electrode pattern.
 16. Asemiconductor device according to claim 14, wherein said insulatorsubstrate comprises on the substrate at least one inter-layer electrodepattern without exposing the end surface having the same electricalpotential as the main current electrode pattern formed on the mainsurface of the substrate.
 17. A semiconductor device according to claim14, wherein in at least one of the terminals the distance between theend of the terminal connected with said electrode terminal and the endof the electrode pattern on the insulator substrate corresponding tosaid terminal is substantially larger than twice of the sum of thethickness of the member constructing the terminal and the thickness ofsaid electrode pattern.
 18. A semiconductor device according to claim14, wherein the main external electrodes are arranged parallel to thedirection of the shorter side of the semiconductor device.
 19. Asemiconductor device according to claim 14, wherein two of the maincurrent terminals are arranged within the gelatin in crossing to eachother and spacing in the height direction, the raising portions from theinside of the gelatin to the external electrodes being in parallel toeach other.
 20. A semiconductor device according to claim 14, wherein anauxiliary terminal for connecting a resistor is provided in the inputterminal.
 21. A semiconductor device according to claim 14, wherein theterminals in the space above the surface of said gelatin are coveredwith a material equivalent to the material making said cutoff member.22. A semiconductor device according to claim 14, wherein the memberscomposing said terminals and another of said cutoff member are bondedwith a hard resin.
 23. A semiconductor device according to claim 14,wherein said cutoff member and the terminals are molded as a unit orbonded with a hard resin.
 24. An inverter device for electric powerusing the semiconductor device according to claim
 1. 25. A circuit boardcomprising: an insulator plate; a first conductor layer provided on oneof the surfaces of the insulator plate; a second conductor layerprovided in a position facing to the first conductor layer on theinsulator plate; and a conductor electrically connecting the firstconductor layer and the second conductor layer.
 26. A circuit boardaccording to claim 25, which comprises a dielectric interposed betweensaid first conductor layer and said second conductor layer.
 27. Acircuit board according to claim 25, wherein the position of the endportion of said second conductor layer is at the position of the endportion of said first conductor layer or at the position between the endportion of said first conductor layer and the end portion of saidinsulator plate.
 28. A circuit board according to claim 25, wherein saidsecond conductor layer comprises a layer selected from the groupconsisting of a metallized layer of tungsten, a metallized layer ofmolybdenum and manganese, a layer plated over a metallized layer oftungsten, a layer plated over a metallized layer of molybdenum andmanganese.
 29. A circuit board comprising: an insulator plate; a firstconductor layer provided on one of the surfaces of the insulator plate;a second conductor layer provided in separating from the first conductorlayer on the insulator plate; and a conductor electrically connectingthe first conductor layer and the second conductor layer.
 30. A circuitboard comprising: an insulator plate; a conductor layer placed on thesurface of the insulator plate; a dielectric layer provided in a gapportion between the insulator plate and the conductor layer; wherein thefollowing relationship exists among the dielectric constant of thedielectric layer ∈_(g), the dielectric constant of the insulator plate∈_(b), the thickness of the gap portion L_(g), and the thickness of theinsulator plate L_(b), ∈_(g)≧∈_(b)×(L_(g)/L_(b)).
 31. A semiconductormodule mounting a plurality of semiconductor elements of the same kind,which comprises: a substrate made of an insulator; said plurality ofsemiconductor elements arranged on said insulator substrate; externalconnecting terminals electrically connected to an external apparatus; aconductor pattern formed on said insulator substrate, jointed with saidexternal connecting terminals as well as electrically connected with theelectrodes of said plurality of semiconductor elements in parallel toform a current path from said external connecting terminals to saidplurality of semiconductor elements; wherein said conductor pattern isformed symmetrically in regard to a certain phantom line on saidinsulator substrate, a plurality of positions on said phantom line andsymmetrical in regard to said phantom line being used as jointing zonesfor said external connecting terminal, current bypass portions to makethe individual current paths of said plurality of semiconductor elementsin a nearly equal length being provided, the current bypass portionbeing formed by cutting away a path between a semiconductor element andsaid jointing zone and providing a bypass for allowing current to flowbetween the semiconductor element and said jointing zone when thedistance between the electrode of the semiconductor element and saidjointing zone is shorter than the distances between the electrodes ofthe other semiconductor elements and said jointing zones (in a casewhere the semiconductor element has plural electrodes or an expandedelectrode the averaged distance being taken as said distance between theelectrode of the semiconductor element and said jointing zone.)
 32. Asemiconductor module according to claim 31, wherein three of saidsemiconductor elements of the same kind are mounted, one specialsemiconductor element among said three semiconductor elements beingarranged so that the center of weight is placed on said phantom line,the other two semiconductor elements being arranged so that the centersof weight each are placed symmetrically each other in regard to saidphantom line and at the corners each in the base of an isoscelestriangle having the center of weight of said special semiconductorelement as the vertex.
 33. A semiconductor module mounting a pluralityof semiconductor elements of the same kind, which comprises: a substratemade of an insulator; said plurality of semiconductor elements arrangedon said insulator substrate; external connecting terminals electricallyconnected to an external apparatus; a conductor pattern formed on saidinsulator substrate, jointed with said external connecting terminals aswell as electrically connected with the electrodes of said plurality ofsemiconductor elements in parallel to form a current path from saidexternal connecting terminals to said plurality of semiconductorelements; wherein said external connecting terminal comprises a facingportion on said conductor pattern, the facing portion being parallel toand facing to the zone of each of the current paths for each of saidsemiconductor elements, the direction of current flow in the facingportion being opposite to the direction of current flow in each of thecurrent paths.
 34. A semiconductor module according to claim 33, whereinsaid plurality of semiconductor elements are arranged in a straight lineon said substrate, said conductor pattern being formed in the intervalfrom the semiconductor element in one end among said plurality ofsemiconductor elements arranged in a straight line to the semiconductorelement in the other end along said plurality of semiconductor elements,said external connecting terminal being jointed to the portion in theside of said semiconductor element in one end of said conductor pattern,said facing portion extending in the direction arranging said pluralityof semiconductor elements from a position corresponding to the positionof said semiconductor element in one end to a position corresponding tothe position of said semiconductor element in the other end.
 35. Asemiconductor module according to claim 31, wherein each of saidplurality of semiconductor elements individually has an input electrodefor allowing current to flow into and an output electrode for allowingcurrent to flow out as said electrodes, an input side connectingterminal for allowing current to flow into from an external apparatusand an output side connecting terminal for allowing current to flow outbeing provided as said external connecting terminals, an input sideconductor pattern jointed with said input side connecting terminal andelectrically connected with the input electrodes of said plurality ofsemiconductor elements in parallel and an output side conductor patternjointed with said output side connecting terminal and electricallyconnected with the output electrodes of said plurality of semiconductorelements in parallel being provided as said conductor pattern, saidinput side connecting terminal and said output side terminal being facedto each other with a space, having parallel input/output facingportions.
 36. A semiconductor module according to claim 35, wherein thegap between said input/output facing portions of said input sideconnecting terminal and said input/output facing portions of said outputside connecting terminal is shorter than 10 mm.
 37. A semiconductormodule according to claim 31, wherein said plurality of semiconductorelements are bipolar transistors, each of the semiconductor elementhaving an input electrode for allowing current to flow into and anoutput electrode for allowing current to flow out as said electrodes anda control electrode for applying voltage for controlling the quantity ofcurrent flowing from said input electrode to said output electrode, aninput side connecting terminal for allowing current to flow into from anexternal apparatus and an output side connecting terminal for allowingcurrent to flow out and a control connecting terminal for applyingvoltage from an external apparatus being provided as said externalconnecting terminals, an input side conductor pattern jointed with saidinput side connecting terminal and electrically connected with the inputelectrodes of said plurality of semiconductor elements in parallel andan output side conductor pattern jointed with said output sideconnecting terminal and electrically connected with the outputelectrodes of said plurality of semiconductor elements in parallel and acontrol conductor pattern jointed with said control connecting terminaland electrically connected with said control electrodes of saidplurality of semiconductor elements in parallel being provided as saidconductor pattern, said control connecting terminal being formed andarranged so that the control connecting terminal does not cross withsaid input side connecting terminal and said output side connectingterminal, and the distance from said control connecting terminal to saidinput side connecting terminal and said output side connecting terminalis longer than the distance between said input side connecting terminaland said output side connecting terminal.
 38. A semiconductor moduleaccording to claim 37, wherein a diode element having an input electrodefor allowing current to flow into and an output electrode for allowingcurrent to flow out is provided, the input electrode of said diodeelement being electrically connected with said input side conductorpattern, the output electrode of said diode element being electricallyconnected with said output side conductor pattern, the jointing zone ofsaid input side connecting terminal on said input side conductor patternbeing placed at a position where the length of the current path fromsaid jointing zone to the input electrode of said diode element isshorter than the length of the current path from said jointing zone tosaid input electrode of said bipolar transistor.
 39. A semiconductormodule according to claim 31, wherein said external connecting terminalhas a bending portion at which the extension of said external connectingterminal in a certain direction turns to the extension of said externalconnecting terminal in the direction opposite to said certain direction.40. A semiconductor module according to claim 39, which comprises ametallic wire connecting said conductor pattern and the electrode ofsaid semiconductor element, said bending portion of said externalconnecting terminal being formed so as not to be placed over/under saidmetallic wire.
 41. A semiconductor module according to claim 31, whichcomprises a casing for covering said insulator substrate so that a spaceis formed in the arranging side of said semiconductor element and saidconductor pattern on said insulator substrate, silicone gel for fillingsaid space of said casing, said silicone gel filling said space so thatan air layer is formed inside said space of said casing.